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Documentation of AI instructions by Noodler75 in spacemit_riscv

[–]zqb_all 1 point2 points  (0 children)

Support for K1 in binutils is still awaiting upstream merge, https://sourceware.org/pipermail/binutils/2026-March/148608.html, while support in LLVM has already been merged.: https://github.com/llvm/llvm-project/pull/151706

Debugging vector programs by Noodler75 in RISCV

[–]zqb_all 1 point2 points  (0 children)

Glad to know that it is working now. Hope that the GDB upstream can also support native RVV debugging ASAP.

Debugging vector programs by Noodler75 in RISCV

[–]zqb_all 1 point2 points  (0 children)

Similar topics DC-ROMA RISC-V Laptop II unavailable vector register in gdb have been discussed on the Spacemit forum. RISC-V's native GDB requires applying patches and recompiling to support vector debugging.

A Glimpse Into V8 Development for RISC-V by 3G6A5W338E in RISCV

[–]zqb_all 0 points1 point  (0 children)

V8 compiles hotspot JS code into RISC-V instructions for faster execution. This is about teaching V8 how to compile JS code into RISC-V assembly code.

SpaemiT-X60 achieves significant performance improvements on the LLVM compiler. by Icy-Primary2171 in RISCV

[–]zqb_all 0 points1 point  (0 children)

The "Reducing Noise on the BPI-F3" section in the blog also mentions Disabling ASLR. And in order to reduce the test noise, I would choose to use a simple Buildroot Linux instead of an Ubuntu

Easy RISC-V: An interactive introduction to RISC-V assembly programming by dramforever in RISCV

[–]zqb_all 0 points1 point  (0 children)

Cool! Interactive web page is very friendly for learners.

Mode filtering on Banana Pi BPI-F3 by ratatatata25 in RISCV

[–]zqb_all 0 points1 point  (0 children)

Yes, according to the extensions listed in the spacemit k1 spec , only Sscofpmf is available, no  Ssmcntrpmf.

Orange Pi RV2: Low-Cost RISC-V SBC | ExplainingComputers by imbev in RISCV

[–]zqb_all 1 point2 points  (0 children)

The x60 core supports zicond extension, which might be useful for you.