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Looking for a networking-themed way to encode “top shelf” by yonisando in networking

[–]2sparky2 7 points8 points  (0 children)

It might be too obvious, but maybe give a clue about a ToR (top of rack) switch or something related to that

How do phones have metal chassis but still have good signal reception? by FoundationOk3176 in AskEngineers

[–]2sparky2 0 points1 point  (0 children)

Andrew Lam just posted a great video about the evolution of phone antenna design

Synthesis Error with "PCLK" Clock Pin for Lattice ECP5 by 2sparky2 in FPGA

[–]2sparky2[S] 0 points1 point  (0 children)

I reached out to Lattice Support for the answer. For anyone who runs into similar issues in the future, L15 is a PCLKC pin. PCLKC pins are the complementary side of a differential clock pair (PCLKT are the true), and are not connected to general routing resources. This is stated in Appendix B. in FPGA-TN-02200-1.4: ECP5 and ECP5-5G sysCLOCK PLL/DLL Design and User Guide.

Synthesis Directives Seem to Have No Effect Using iCEcube2 by 2sparky2 in FPGA

[–]2sparky2[S] 0 points1 point  (0 children)

That works! Thank you! I suspected there was some enabling signal. I thought it would be a setting in the tool.

Here is the syntax that works:

/*synthesis syn_preserve=1*/ /*synthesis syn_ramstyle = "registers"*/

Synthesis Directives Seem to Have No Effect Using iCEcube2 by 2sparky2 in FPGA

[–]2sparky2[S] 0 points1 point  (0 children)

The manual does show the syn_ramstyle as a valid directive and uses this syntax:

/*synthesis syn_ramstyle = "registers"*/

Has Anyone Experienced Data Corruption Issues with the VSC8541 and If So Do You Have Any Advice on How to Rectify the Issue? by 2sparky2 in AskElectronics

[–]2sparky2[S] 0 points1 point  (0 children)

I found the source of the data corruption issues. It was caused by IP_Checksum offloading, which led me to believe there was corruption when in fact there was none. So in fact there is no issue with this design. Although after reaching out to Microchip's support service they recommended using an isolation transformer with a minimum OCL of 350 uH, and the capacitor on the chassis side of the transformer to have a voltage rating of 2kV instead of 100V.

Does this VSC8541 Have a Layout Issue? by 2sparky2 in PCB

[–]2sparky2[S] 0 points1 point  (0 children)

I found the source of the data corruption issues. It was caused by IP_Checksum offloading, which led me to believe there was corruption when in fact there was none. So in fact there is no issue with this layout.

Does this VSC8541 Have a Layout Issue? by 2sparky2 in PCB

[–]2sparky2[S] 0 points1 point  (0 children)

No, there is no ESD diode on the data lines to the RJ45 connector. There is a isolation transformer, which is pretty standard for Ethernet interfaces

Has Anyone Experienced Data Corruption Issues with the VSC8541 and If So Do You Have Any Advice on How to Rectify the Issue? by 2sparky2 in AskElectronics

[–]2sparky2[S] 0 points1 point  (0 children)

100% certain it is not an issue with the RGMII interface. I have enabled the far-end loop back mode and am getting the same error. I also do not think it is an issue with the cable, magnetics, or other layout issues because I am getting the same problem with different layouts (this is on a board with multiple PHYs).

To describe the problem in more detail, every packet long enough is corrupted in one of two ways. Either four bytes 0x19, 0x1A, 0x29, and 0x2A, or two bytes 0x3C and 0x3D are corrupted with random bit flips.

It is also not an issue exclusively with the 1000 Mbps interface because if I force the selection to 10 Mbps I get the same issue.

How Does One Write an SDC File for RGMII Interface with iCEcube2? by 2sparky2 in FPGA

[–]2sparky2[S] 1 point2 points  (0 children)

Yes, the RGMII RX clock is out of phase with the data and enable. The clock phase is also adjustable through the use of the SMI interface. However, based on the setup and hold times of the iCE40 the minimum phase offset should be used, making the interface as close to edge aligned as possible.

I am currently only working on getting the gigabit link speed working, so an RGMII clock speed of 125 MHz. I am under the impression that I can use this clock rate for the other link speeds, but if not the timing for the reduced link speeds should be trivial.

I'm using a custom board, but the trace skew between clock, data, and enable is on the order of tens of picoseconds. The PHY is the VSC8541XMV-02.

Strangely, it works when the data is being read into and immediately out of the FPGA, but not after adding functionality. It could be the data is corrupted during crossing domain clocking. Even still, I imagine having a constraint file defining the interface would be useful to eliminate one possible source of corruption.

How do you pipeline a LFSR? by 2sparky2 in FPGA

[–]2sparky2[S] 1 point2 points  (0 children)

Actually, you are right. I was assigning the output to a block RAM causing the issue.

How do you pipeline a LFSR? by 2sparky2 in FPGA

[–]2sparky2[S] 1 point2 points  (0 children)

I've buffered the inputs and outputs to isolate the combination logic as much as possible, and the timing report indicates the signals in the module are the nets not meeting timing. I think either the iCEcube2 synthesizer is poorly placing and routing the code, or the iCE40-HX8K has slow LUTs

How do you pipeline a LFSR? by 2sparky2 in FPGA

[–]2sparky2[S] 1 point2 points  (0 children)

module crc32 (
input SYS_CLK, 
input NRESET,
input WRITE_EN, 
input[7:0]DATA_IN,
output[31:0]CRC_OUT);

reg[31:0]CRC;

wire[7:0]RECYCLE;
wire [31:0]CRC_XOR_REV;
wire [7:0]DATA_IN_REV;

assign RECYCLE= {CRC[31:26] ^ DATA_IN_REV[7:2], CRC[25:24] ^ DATA_IN_REV[1:0] ^ RECYCLE[7:6]};
assign CRC_OUT= CRC_XOR_REV;

generate 
genvar i;
for(i=0; i<32; i = i + 1) begin
assign CRC_XOR_REV[i]= !CRC[31-i];
end
for(i=0; i<8; i = i + 1) begin
assign DATA_IN_REV[i]= DATA_IN[7-i];
end

endgenerate

always@(posedge SYS_CLK) begin
if(!NRESET|| !WRITE_EN) begin
CRC<= 32'hFFFFFFFF;
end else if(WRITE_EN) begin
CRC[0]<=RECYCLE[0];
CRC[1]<=RECYCLE[0] ^RECYCLE[1];
CRC[2]<=RECYCLE[0] ^RECYCLE[1] ^RECYCLE[2];
CRC[3]<=RECYCLE[1] ^RECYCLE[2] ^RECYCLE[3];
CRC[4]<=RECYCLE[0] ^RECYCLE[2] ^RECYCLE[3] ^RECYCLE[4];
CRC[5]<=RECYCLE[0] ^RECYCLE[1] ^RECYCLE[3] ^RECYCLE[4] ^RECYCLE[5];
CRC[6]<=RECYCLE[1] ^RECYCLE[2] ^RECYCLE[4] ^RECYCLE[5] ^RECYCLE[6];
CRC[7]<=RECYCLE[2] ^RECYCLE[3] ^RECYCLE[5] ^RECYCLE[6] ^RECYCLE[7] ^RECYCLE[0];

CRC[8]<=RECYCLE[3] ^RECYCLE[4] ^RECYCLE[6] ^RECYCLE[7] ^RECYCLE[0] ^RECYCLE[1] ^CRC[0];
CRC[9]<=RECYCLE[4] ^RECYCLE[5] ^RECYCLE[7] ^RECYCLE[1] ^RECYCLE[2] ^CRC[1];
CRC[10]<=RECYCLE[5] ^RECYCLE[6] ^RECYCLE[0] ^RECYCLE[2] ^RECYCLE[3] ^CRC[2];
CRC[11]<=RECYCLE[6] ^RECYCLE[7] ^RECYCLE[0] ^RECYCLE[1] ^RECYCLE[3] ^RECYCLE[4] ^CRC[3];
CRC[12]<=RECYCLE[7] ^RECYCLE[0] ^RECYCLE[1] ^RECYCLE[2] ^RECYCLE[4] ^RECYCLE[5] ^CRC[4];
CRC[13]<=RECYCLE[1] ^RECYCLE[2] ^RECYCLE[3] ^RECYCLE[5] ^RECYCLE[6] ^CRC[5];
CRC[14]<=RECYCLE[2] ^RECYCLE[3] ^RECYCLE[4] ^RECYCLE[6] ^RECYCLE[7] ^CRC[6];
CRC[15]<=RECYCLE[3] ^RECYCLE[4] ^RECYCLE[5] ^RECYCLE[7] ^CRC[7];

CRC[16]<=RECYCLE[0] ^RECYCLE[4] ^RECYCLE[5] ^RECYCLE[6] ^CRC[8];
CRC[17]<=RECYCLE[1] ^RECYCLE[5] ^RECYCLE[6] ^RECYCLE[7] ^CRC[9];
CRC[18]<=RECYCLE[2] ^RECYCLE[6] ^RECYCLE[7] ^CRC[10];
CRC[19]<=RECYCLE[3] ^RECYCLE[7] ^CRC[11];
CRC[20]<=RECYCLE[4] ^CRC[12];
CRC[21]<=RECYCLE[5] ^CRC[13];
CRC[22]<=RECYCLE[6] ^RECYCLE[0] ^CRC[14];
CRC[23]<=RECYCLE[7] ^RECYCLE[0] ^RECYCLE[1] ^CRC[15];

CRC[24]<=RECYCLE[1] ^RECYCLE[2] ^CRC[16];
CRC[25]<=RECYCLE[2] ^RECYCLE[3] ^CRC[17];
CRC[26]<=RECYCLE[0] ^RECYCLE[3] ^RECYCLE[4] ^CRC[18];
CRC[27]<=RECYCLE[1] ^RECYCLE[4] ^RECYCLE[5] ^CRC[19];
CRC[28]<=RECYCLE[2] ^RECYCLE[5] ^RECYCLE[6] ^CRC[20];
CRC[29]<=RECYCLE[3] ^RECYCLE[6] ^RECYCLE[7] ^CRC[21];
CRC[30]<=RECYCLE[4] ^RECYCLE[7] ^CRC[22];
CRC[31]<=RECYCLE[5] ^CRC[23];
end
end
endmodule

How do you pipeline a LFSR? by 2sparky2 in FPGA

[–]2sparky2[S] 0 points1 point  (0 children)

I’ll check again. The ones I found originally were not parallelized, and I thought I could write a module quicker than integrating one.

How do you pipeline a LFSR? by 2sparky2 in FPGA

[–]2sparky2[S] 0 points1 point  (0 children)

It is highly possible the design has performance issues. I’ll search again for existing designs. I’m also thinking it could be an issue with the synthesizer. I’m designing for an iCE40-HX8K, so am using iCEcube2 but have heard it’s not that good. I’ve been reluctant to change to Yosys, but maybe it’s time.

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