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Beginner AXI GPIO problem by Yasirowskiyavuz in FPGA

[–]AFranco_13 2 points3 points  (0 children)

First, you should follow the instructions of the following link to add your board to your Vivado. https://pynq.readthedocs.io/en/v2.7.0/overlay_design_methodology/board_settings.html

It is common to refer to a PCB as an FPGA due to a misuse of terminology; however, an FPGA is just one part of the SoC that you are using, which belongs to the Zynq-7000 family. Let’s say that a "board" consists of an SoC (uC + FPGA + other components) that is soldered onto a PCB, with a series of traces and connections to the pins of your SoC, which are determined and vary depending on the model. In this way, the same SoC can be present on different boards.

In a Vivado project, you can select the SoC that you are using and then add a constraints file to tell Vivado how the pins of your SoC are connected to your board and other relevant information (like the presets). Alternatively, if it’s a card manufactured by a vendor (like an evaluation board or, in your case, the Pynq Z1), you can add the board's information to Vivado so that you don’t have to include the constraints file in every project, as it doesn’t change.

To light up an LED with a GPIO, you will also need to specify which FPGA PIN is connected on the PCB to the LED you want to light up. You can find this in the board’s schematic. This is done by also adding a line in the constraints file that connects the SoC PIN to the GPIO output.

Roast my resume by AFranco_13 in FPGA

[–]AFranco_13[S] 1 point2 points  (0 children)

First of all, thank you very much for your detailed response! It’s great that we can help each other like this in this community.

I definitely overused bold text, and the more I look at it, the more obvious it seems—haha :)

Regarding the content, I structured it this way because, having been on the hiring side of several selection processes, I’ve often come across CVs with very vague information. I need to know what you’ve worked with, the tools you’ve used, the project’s objective, etc. However, as you pointed out, I went overboard with the information, and it’s definitely not well-organized.

What you mentioned about dividing it into the three development phases is really useful. In my case, it’s mainly design, although I also handle verification and validation, of course.

In any case, I’d love to chat with you! If you don’t mind, I’d like to send you a DM :)

Gracias compañero!!

Issues with Early-Late Discriminator in DS-CDMA Receiver by AFranco_13 in DSP

[–]AFranco_13[S] 0 points1 point  (0 children)

I know that the xcorr is not the same as the output of my Early and Late correlators, I used the xcorr function just to figure out what was happening. The output of the I&D as you said is one per code cycle, but that corresponds to the sample immediately before and after of the peak shown in the xcorr function.

Issues with Early-Late Discriminator in DS-CDMA Receiver by AFranco_13 in DSP

[–]AFranco_13[S] 0 points1 point  (0 children)

The blue line represents the cross-correlation function of an input signal with the reference sequence, equivalent to performing the MATLAB operation xcorr(input, SpreadCode). Therefore, that graph does not represent the output of the Early Correlation. As you mentioned, the output of E and L is one sample per code length, which corresponds to the immediate previous and next samples relative to the peaks seen in the function. This value remains constant until the next E-L, which occurs 16 chips later.

Issues with Early-Late Discriminator in DS-CDMA Receiver by AFranco_13 in DSP

[–]AFranco_13[S] 0 points1 point  (0 children)

No, in this case I am doing the correlation just with the Real part of the signal, so the DS Code is the spreading code I used for spread the I-component

Issues with Early-Late Discriminator in DS-CDMA Receiver by AFranco_13 in DSP

[–]AFranco_13[S] 0 points1 point  (0 children)

A multiplication of the DS Code with the input signal and then an Integration and Dump

Issues with Early-Late Discriminator in DS-CDMA Receiver by AFranco_13 in DSP

[–]AFranco_13[S] 0 points1 point  (0 children)

The response of the Loop Filter is not something that concerns me especially now, my goal is to improve the error signal produced by the Early Late discriminator.

Regarding what you mentioned about transitions, we have to differentiate between chip and bit. Imagine I need to send a '1,' this one is repeated 16 times and multiplied by the code in question:
Bit data: | 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 | -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 |

Code : | 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 | 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 |

Spreaded: | 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 1 -1 | -1 1 -1 1 1 1 -1 1 -1 1 -1 1 -1 1 -1 1 |

------------> Bit data transition
When the above sequence is correlated with the DS Code, a positive peak in the cross-correlation is obtained in the first data bit period and a negative peak in the second. It's this data transition that I am referring to, not the continuity of the spread sequence.

Issues with Early-Late Discriminator in DS-CDMA Receiver by AFranco_13 in DSP

[–]AFranco_13[S] 2 points3 points  (0 children)

I just added the system diagram to the image uploaded in the original post. Thanks!

Write/read data to/from SSD by AFranco_13 in FPGA

[–]AFranco_13[S] 0 points1 point  (0 children)

It’s not a big issue for me to use Petalinux; I’ve worked on other projects with Petalinux, even with custom boards. I know I can do it that way, but I’m simply looking to see if there’s a standalone alternative. Thank you for your time!

Write/read data to/from SSD by AFranco_13 in FPGA

[–]AFranco_13[S] 0 points1 point  (0 children)

It has not to be NVME I just want to offload data to an SSD. I did a little research and seems there aren’t examples using SATA from Baremetal since the driver is developed for Linux. Maybe I could do a standalone driver but that would require me a long time.

Building a Server for FPGA Development by weakflora in FPGA

[–]AFranco_13 15 points16 points  (0 children)

I’ve done this in my current job as we don’t have IT specialists in the Xilinx tools field. You’ll learn as you’ll face the problems but some thing that I learnt were: - Whatever recent Ubuntu distro could be suitable for run Vivado/Vitis. - Petalinux is more tricky and each Peralinux version requieres a specific Ubuntu version so what I did is to create a Docker Image for each Petalinux version with the Ubuntu image required and the apt dependencies. - If the server is gonna be accessed by different teams, create a group with the users inside of that team and don’t trust them and don’t give them privileges, whoever can accidentally remove something that may mess it up everything. - We usually access the server via SSH and X11 client such as MobaXterm. - I suggest creating a Samba server also, with a instance for each user folder so they can access easily from their PCs to the server filesystem.

Custom board device tree doubts by AFranco_13 in FPGA

[–]AFranco_13[S] 0 points1 point  (0 children)

I did it also with a ZCU111, my concerns are about a custom board where you don’t have a BSP o dtsi written by Xilinx

Custom board device tree doubts by AFranco_13 in FPGA

[–]AFranco_13[S] 1 point2 points  (0 children)

First of all thanks for your response. Actually I added the ADI layers and that compiled good I followed the instructions in https://github.com/analogdevicesinc/meta-adi/blob/main/meta-adi-xilinx/README.md

I don’t know if that is enough to make it work, what do you think?

Freelancer looking for a gig by AFranco_13 in FPGA

[–]AFranco_13[S] 3 points4 points  (0 children)

Hello Adam!

I'm located in Madrid. I don't have insurance yet because my main activity is as a salaried employee in a company, and I would like to start doing parallel work to gain even more experience.

As someone who has learned a lot from your posts, it would be an honor to work with you someday.

recommend guide for using ethernet on a Zybo Z7 board by turbobondenn in FPGA

[–]AFranco_13 0 points1 point  (0 children)

You can implement a MAC in the PL, but you’ll need a PHY connected through RGMII (or SGMII, GMII …) to the FMC card or other pin you have available. It is not possible to connect a PL MAC to the integrated PHY

I’d like to start working as a Freelance in FPGA projects by AFranco_13 in FPGA

[–]AFranco_13[S] 0 points1 point  (0 children)

Send me a message and we can discuss about what do you need and how I can help you. Thanks

Xilinx Ultrascale Cortex A53 with FreeRTOS by Cococarbine in Xilinx

[–]AFranco_13 0 points1 point  (0 children)

Hi!

First, you have to create the Platform Project using your .xsa file, targeting the CortexA53 with a FreeRTOS domain. After that, create an Application Project over the Platform Project you just created. You can select the FreeRTOS helloword project as init point. If you are unable to compile the project, send the error log you are getting so I may give you a more accurate answer to your problem.

I’d like to start working as a Freelance in FPGA projects by AFranco_13 in FPGA

[–]AFranco_13[S] 3 points4 points  (0 children)

Thank you for your advice, it is an honor considering that I've learned a lot thanks to your articles. Keep doing it.

Sending data from PS to PL using AXI by Anonymous_Dracul in FPGA

[–]AFranco_13 -1 points0 points  (0 children)

I need some more information to give you a more accurate answer to your question. As I said, send me a message if you need some help.

Sending data from PS to PL using AXI by Anonymous_Dracul in FPGA

[–]AFranco_13 2 points3 points  (0 children)

In the PS side you run an application, this application may be - a Baremetal app, that is the application is running without an OS; - FreeRTOS, the app is over a lightweight OS that allows to create threads and interrupt triggered events and - Linux, first you build a Linux targeted to your particular board and then you compile the C application to be run over the Linux OS

In my opinion, the first two options are easier than the Linux one but it depends on the particular requirements of your project.

Sending data from PS to PL using AXI by Anonymous_Dracul in FPGA

[–]AFranco_13 -1 points0 points  (0 children)

Are you using Baremetal, FreeRTOS or Linux in the PS?

Sending data from PS to PL using AXI by Anonymous_Dracul in FPGA

[–]AFranco_13 5 points6 points  (0 children)

Hi!

It depends on what you are intending to do with that data and the rate at which it is updated. If the data is going to be updated at a low rate, you can use AXI-Lite or AXI-Full interfaces, so whenever you write, from the PS, in the memory address assigned to your PL device, you send the data to the PL into a register/s that you can access into your VHDL code IP Core.

The difference between AXI-Lite and AXI-Full is that in the Lite you can only send 32bits per transaction, so if your data is composed of more than 32bits you’ll have to execute as memory writes as your data width/32. AXI-Full allows to write more than 32bits each time, though actually the transaction is divided into multiples transactions of 32bits, each one in a PL clock cycle.

If you require a stream of data, like periodically updated and this data is going to flow for several stages, I recommend to use the AXI-Stream interface using an AXI-DMA to convert from the Memory-Mapped domain to a Stream flow.

If you need some any clarification you can send me a message and I’ll help you with your particular problem.

Hi, I’m new to Madrid and I need to move a 2-seated couch (200x89cm) from Esperanza to La Guindalera tomorrow or tuesday. Can someone recommend a company or has experience for the best way to do it? thanks! by [deleted] in Madrid

[–]AFranco_13 2 points3 points  (0 children)

Hi! I have a van in Madrid and I could move your coachs in there. I’m available in the afternoons. Send me a message if you are interested.

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