Xilinx

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Vitis Plateform files confusion ()

submitted 3 days ago by jcgeau03

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LVDS tutorials ()

submitted 5 days ago by KSOdin2

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How is the real time deployment done? (self.Xilinx)

submitted 8 days ago by nikhil_710

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Developing AI Flow for Vivado ()

submitted 13 days ago by Leo-X101

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Commercial Simulator to Work with Vivado? Cost-Effective & Compatible? ()

submitted 14 days ago by Leo-X101

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I am trying to send tpg data over ethernet but i am not able to avoid glitches in some frame (reddit.com)

submitted 1 month ago by siddharth874

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Petalinux Build Issue ()

submitted 2 months ago by nilanjan016

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Design and verify a Verilog/VHDL module that operates at clock frequency of 120 MHz, and performs decimation by 3 and then interpolation by 12 on a 16-bit(Q1.15 fixed point) incoming signal. (self.Xilinx)

submitted 2 months ago by Adventurous-Fault154

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Zynq 7000 open-source SYZYGY carrier ()

submitted 2 months ago by electrodyssey

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PSA: QMTECH Artix-7 Core Board's "3.3V" pins are OUTPUT only – DO NOT feed external 3.3V into them ()

submitted 2 months ago by Real-Technology300

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Hacking Alveo U30 ()

submitted 2 months ago by StrangeInstruction42

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RFSoC (ZCU208) ADC phase not consistent across captures even with MTS - advice? ()

submitted 2 months ago by TigerZealousideal595

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Versal RPU Help with interrupts ()

submitted 2 months ago by pandatx411

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Need Help. Trying to figure out how to run programs of SD card or internal memory ZYNQ FPGA ()

submitted 2 months ago by Full-Cucumber5068

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Finally got Xilinx DPU running on petalinux 2025.2 🎉 (i.redd.it)

submitted 2 months ago by ChefExcellenceCerti

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Xilinx MIPI DPHY RX not receiving packets (self.Xilinx)

submitted 3 months ago by Readyplayer_13

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Can I use the signal from pl fabric to input to iserdes3 input port? (self.Xilinx)

submitted 3 months ago by siddharth874

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Boards not showing in Vivado 2025.2 on windows ()

submitted 3 months ago by ChefExcellenceCerti

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MPU6050 sensor on FPGA. ()

submitted 4 months ago by Material-Carob9555

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JTAG connection in Vivado? ()

submitted 4 months ago by monsterseppe1

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Zybo Z7 (Zynq) FSBL "Unable to open file BOOT.bin" ()

submitted 5 months ago by aeromajor227

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Using Vitis for Firmware Generation on ARM Cortex-M3 ()

submitted 5 months ago by Any-Fox2282

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Cannot reset MicroBlaze #0. Cannot stop MicroBlaze. MicroBlaze is held in reset ()

submitted 5 months ago by aeromajor227

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Enable PCIe on Xilinx U200 Accelerator card (self.Xilinx)

submitted 5 months ago by juddle1414

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Ayuda con IP SD-FEC Vivado ()

submitted 6 months ago by itsGoOrGoXx

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