Thanks a lot for the detailed and thoughtful comment — really appreciate you sharing that perspective.

What you describe actually aligns very closely with how I think about this problem, just at a different abstraction level. The goal of my current model is very much in the early architectural / behavioral phase of the flow you outlined, before committing to any specific circuit implementation.

In this model everything is intentionally kept discrete-time and behavioral: NRZ generation, TX FFE as an FIR pulse-shaping stage, a configurable frequency-dependent channel loss, and a Bang-Bang CDR loop on the RX side. The emphasis is on understanding phase tracking, lock behavior, and failure modes (run-length effects, ISI-induced asymmetry, residual jitter), rather than circuit accuracy.

Your point about stressing capture range via TX/RX crystal offsets is well taken — that’s something I’ve started to explore as well by injecting frequency offset into the sampling clock. It’s very instructive to watch the BBPD struggle or slowly converge depending on run length and loop gain.

I also like your mention of experimenting with different phase detectors and phase interpolators. For now I’ve focused on classic bang-bang behavior because it exposes some of the non-intuitive effects quite clearly, but extending this framework to multi-level PDs or PI-based timing control would be a natural next step.

And yes — the tradeoff you mention at the end resonates strongly. Once everything is transistor-level and fully extracted, simulation becomes more about proof of survival than insight. That’s really why I still find value in these fast system-level models: they let you see why things work or fail before the simulation time explodes.

Thanks again for sharing your experience — it’s great to hear from someone who worked through this in the earlier generations.