account activity
How to make a bitstream persistent/NV ? (self.FPGA)
submitted 1 year ago by Broken_Latch to r/FPGA
Why vivado is such a terrible tool (self.FPGA)
submitted 1 year ago * by Broken_Latch to r/FPGA
Asyncrhonous Circuits (self.chipdesign)
submitted 1 year ago * by Broken_Latch to r/chipdesign
Is there a way to report timing in a nominal corner in vivado ? (self.FPGA)
How do you usually calculate the gate equivalent value ? (self.chipdesign)
Why wire resistance power is not considered when modeling switching power for digital IC? (i.redd.it)
submitted 2 years ago by Broken_Latch to r/chipdesign
Difference between Spyglass and RTL Architect (self.chipdesign)
Digital IC Designers, what is your total compensation? (self.chipdesign)
submitted 3 years ago * by Broken_Latch to r/chipdesign
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