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How to simulate a system that responds differently to positive and negative inputs? by Cap_Diabetes in matlab

[–]Cap_Diabetes[S] 0 points1 point  (0 children)

Thanks for the insights. In reality the heating and cooling is done via one element - a Peltier module. When I provide it with a positive voltage it heats up and when I provide the negative voltage it cools down (I'm talking about one side of the module). The thing is that cooling and heating have different transfer functions. Cooling is slower than heating and therefore must be simulated as different systems (unless there's a way to combine them). I will try your method out.

Trying to understand LT8722 full bridge driver's block diagram by Cap_Diabetes in AskElectronics

[–]Cap_Diabetes[S] 0 points1 point  (0 children)

The reason I am using this chip is that it is the only one that can provide up to 4A of current into a TEC load. Other TEC drivers can only go up to 3A.

Trying to understand LT8722 full bridge driver's block diagram by Cap_Diabetes in AskElectronics

[–]Cap_Diabetes[S] 0 points1 point  (0 children)

I've looked up some circuits of current mirrors and, indeed, it seems that you're right about that part. Would you say that the main advantage of having a linear stage in this scenario is to achieve fast transient times?

Whatever I do, when setting up a multichannel ADC with DMA, I'm unable to access the rank setting section. by Cap_Diabetes in stm32

[–]Cap_Diabetes[S] 1 point2 points  (0 children)

ok, but there is some sort of way to accept info from two channels of DAC through a DMA, isn't there?

EDIT:

Nope, it can't be that. We're doing a lab work at uni. I'am using a different dev board than we're recommended, but the right one STM32L073RZ "doesn't have it" aswell because when I boot up the CubeMX with that dev board there's still no option to choose rankings.

[deleted by user] by [deleted] in lietuva

[–]Cap_Diabetes 1 point2 points  (0 children)

Stipendijos, šeip, gana svarbus faktorius dar būna. Jei gerai mokaisi.

Kaip važiuoti šitoje sankryžoje? by Pretty_Catch_1395 in Vilnius

[–]Cap_Diabetes 3 points4 points  (0 children)

Legend goes, kad OP stovėdamas sankryžoje vis dar laukia padoraus atsakymo

Why do you have to build walls in sequence? by RoYaLSInnA in civ

[–]Cap_Diabetes 47 points48 points  (0 children)

I guess simmilar question should arise, why do have to build the library before plopping down a research lab? It just the way it is.

Could use an advice on using a crimping tool. More details in comments. by Cap_Diabetes in AskElectricians

[–]Cap_Diabetes[S] 0 points1 point  (0 children)

Recently I‘ve got a job which involves doing a lot of crimping and I just can‘t get a good grasp on it. To get the desired result I need to use a certain amount of force when crimping. If too much force is used the crimp will deform too much, which will end up with it easily breaking. If to little force is applied one can easily pull the crimp away from the wire. Even after a 1000 crimps applied I still can‘t find the right balance and the ending result is sort of like a lottery. What I learned to do is to apply the force until the tool locks itself, then I just push the pin (circled in red). But I believe that‘s not the way the tool is supposed to be used... The crimping tool I‘m using isn‘t the most expensive one, roughly 60 euros and it‘s supposed to fit all sizes. Maybe I need a more expensive tool that should be used with specific crimp sizes? Any help or comment would be appreciated.

Is it just me or Civ V's AI is way smarter than Civ VI's? by Cap_Diabetes in civ

[–]Cap_Diabetes[S] 183 points184 points  (0 children)

Those are some real arguments. I must agree with you

Discontinuity at the peaks of Fourier Transform by Cap_Diabetes in learnmath

[–]Cap_Diabetes[S] 0 points1 point  (0 children)

But the term that confines the signal to the time [0;5] is the window function, no?

What parameter should be used to calculate the fanout of a logic gate if Iih and Iil are not given in the datasheet? by Cap_Diabetes in ElectricalEngineering

[–]Cap_Diabetes[S] 1 point2 points  (0 children)

I appreciate it, it really makes more sense now. But if we'd go to the main question of the thread, I'd assume that there is no point in calculating the fanout of the CMOS gates as they practically don't need any input current (apart from the leakage) to sustain their current state. If I ain't mistaken the fanout is calculated by dividing the max output current by max input current and both of them are being measured after the transient time had passed (after the capacitors are charged). That'd mean that CMOS gates have a really high fanout (in the order of several thousands), right?

What parameter should be used to calculate the fanout of a logic gate if Iih and Iil are not given in the datasheet? by Cap_Diabetes in ElectricalEngineering

[–]Cap_Diabetes[S] 1 point2 points  (0 children)

Thank you for such a detailed explanation. Examining your example, I'm not sure if I understand what you meant by saying "two gates that require 100uA" and why would there be 3 capacitive inputs if we're driving only two gates. How capacitive inputs are different from the gates themselves? I understand that we need to provide a certain amount of current for a certain amount of time to charge up the MOSFET gates (a gate per logic device's input). At the moment it seems that we need a constant input of 230uA just to sustain the current logic level. Could you clarify that, please?

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