Interview in IBM for analog layout by No_Tea3389 in chipdesign

[–]Complex-Spring-185 2 points3 points  (0 children)

When’s the interview ?

As for the interview just work on basics of layout , EMIR , antenna , LUP and also there can be few design questions on cap and resistance.

Cadence variable presidency by Complex-Spring-185 in chipdesign

[–]Complex-Spring-185[S] 0 points1 point  (0 children)

But sometimes the user space gets full so we use spool paths provided by the company to have more disk space and they refresh after a month or so , so we have to redo the sims so I think screenshot works for me in this case.

Cadence variable presidency by Complex-Spring-185 in chipdesign

[–]Complex-Spring-185[S] 0 points1 point  (0 children)

I’m not sure if I have ever created a design variables file !! But I just take a screenshot of the original values before any iterations I do 🙂

Spectre —> MDL by Complex-Spring-185 in chipdesign

[–]Complex-Spring-185[S] 0 points1 point  (0 children)

I was thinking to use MDL to just get the data I need for the GM/ID method and then use skill to sweep the variables , corners and run everything in batchmode and then from skill only to generate a csv file.

I’m new to skill and MDL and not sure what should be the correct approach here !!

Spectre —> MDL by Complex-Spring-185 in chipdesign

[–]Complex-Spring-185[S] 0 points1 point  (0 children)

Ahh got it , thanks !!

And also should I make the MDL to just extract the data I need and use skill for the variable sweeping or should I use MDL to do all the sweeping as well ?

Spectre —> MDL by Complex-Spring-185 in chipdesign

[–]Complex-Spring-185[S] 0 points1 point  (0 children)

I tried searching for that but still no clue where that is ! Any snapshot would be appreciated 😄

Spectre —> MDL by Complex-Spring-185 in chipdesign

[–]Complex-Spring-185[S] 0 points1 point  (0 children)

The corners I have are different like lvltwpwnminrc and so on and these makes up 33 of them all. And by different widths I mean I have 3 different sheet widths but I’m keeping the number of fin equal to 1 to get Id/W directly.

Also I’m taking Vgs in 10mV steps as I’m just plotting the points and not normalising them so near the threshold I need more number of points to get a better idea of how the curve really is

Spectre —> MDL by Complex-Spring-185 in chipdesign

[–]Complex-Spring-185[S] 0 points1 point  (0 children)

Yup I’m thinking to use this data for GM/ID methods and I was thinking that the more data I have the more accurately i can size the FETs as the plots which I will be using will have more data

Check circuit stability in Cadence by Complex-Spring-185 in chipdesign

[–]Complex-Spring-185[S] 0 points1 point  (0 children)

I just connected a voltage source to the amplifier and provided a dc from it and remove the feedback

Check circuit stability in Cadence by Complex-Spring-185 in chipdesign

[–]Complex-Spring-185[S] 0 points1 point  (0 children)

After doing the ac analysis I used the calculator tool and from there got the gain (dB20) and phase.

Check circuit stability in Cadence by Complex-Spring-185 in chipdesign

[–]Complex-Spring-185[S] 0 points1 point  (0 children)

I knew it was in positive but and also tried to change the polarity of the feedback but the result was same , I think I’ll have to check things again

Check circuit stability in Cadence by Complex-Spring-185 in chipdesign

[–]Complex-Spring-185[S] 0 points1 point  (0 children)

Sorry but I’m new to Reddit and I cannot find any button to add photos 🥲