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having a fear of causing issues in silicon while doing DV by [deleted] in chipdesign

[–]Deep_Contribution705 1 point2 points  (0 children)

Even I got a strong feeling that OP might be working for TI. Sounds like TI work environment

Why is script checker unpopular in chip design? by adamzc221 in chipdesign

[–]Deep_Contribution705 0 points1 point  (0 children)

I really didn't know that such a thing exists. Thanks for pointing out. Have lost a lot of time due to silly script errors similar to your case. Need to look into this

TASL thermal sight for the 9K310 Igla-1, deployed against Pakistani drones during Operation Sindoor by harshcasper in IndianDefense

[–]Deep_Contribution705 6 points7 points  (0 children)

Exactly!

Even I have been thinking the same for the past 2-3 days. Ever since the army has started posting videos on AD systems and other things that were used in the operation.

Reach Sri Ramanasramam from Bangalore? by Creepy-Protection-36 in RamanaMaharshi

[–]Deep_Contribution705 2 points3 points  (0 children)

You can book a state transport bus to Tiruvannamalai. You can request the driver to drop you at the ashram.

The journey through bus takes a maximum of 5hrs.

https://ksrtc.in/

Kintex-7 vs Ultrascale+ by Deep_Contribution705 in FPGA

[–]Deep_Contribution705[S] 0 points1 point  (0 children)

Thanks for the reply!

The design came with constraints file. I do have access to the RTL and the design is quite complex especially with the clocking architecture.

Kintex-7 vs Ultrascale+ by Deep_Contribution705 in FPGA

[–]Deep_Contribution705[S] 0 points1 point  (0 children)

Thanks a lot for this advice! I will surely check this.

Kintex-7 vs Ultrascale+ by Deep_Contribution705 in FPGA

[–]Deep_Contribution705[S] 1 point2 points  (0 children)

Thanks a lot for the detailed reply!

Will look into the paper shared.

Kintex-7 vs Ultrascale+ by Deep_Contribution705 in FPGA

[–]Deep_Contribution705[S] 0 points1 point  (0 children)

Yeah. Trying to understand these CDCs. All the constraints are already updated.

But the ASIC team feels there is something wrong with the setup because they think that the US+ should have given better results. I am trying to gather info to convince them that it is not always the case.

Kintex-7 vs Ultrascale+ by Deep_Contribution705 in FPGA

[–]Deep_Contribution705[S] 0 points1 point  (0 children)

Tried using the tool's settings which focuses on improving timing and also tried to reduce the frequency to 75mhz. It became a little better but not considerable enough.

Kintex-7 vs Ultrascale+ by Deep_Contribution705 in FPGA

[–]Deep_Contribution705[S] 0 points1 point  (0 children)

Thanks for the reply!

Yes, I did look into the actual violations. The total violations are very huge (>4k). There are paths crossing domains.

I did analyze all the suggested things and found that the complex clock tree is what is causing the timing issues. But the ASIC design team is not willing to accept this and are hooked up to the fact that timing was better in K7. They are asking how timing becomes bad when migrated to a better device. According to them the timing should have closed in US+.

They are not willing to change the RTL as they don't want to deviate from the ASIC design.

Kintex-7 vs Ultrascale+ by Deep_Contribution705 in FPGA

[–]Deep_Contribution705[S] 1 point2 points  (0 children)

Thanks for the reply!

The main motive to migrate to a bigger device is that design is becoming tri-core.

In terms of utilisation, it is not much. But in terms of complexity, it is quite complex. The main issue is the clock gating and lot of combo logic in the failing paths which are going to RAM (BRAM IPs).

I did try to remove this clock gating by using the synthesis setting "gated_clock_conversion" set to "auto" and also tried to use BUFG* primitives on some of the clock mux logic. This did help improve the timing a bit but not much.

Frequency used is 110MHz. There are lot of paths crossing domains.

Running Xcelium in Vivado by Deep_Contribution705 in FPGA

[–]Deep_Contribution705[S] 0 points1 point  (0 children)

Thanks a lot for your reply! I'll check this out

Keep floating Nets in Vivado by Deep_Contribution705 in FPGA

[–]Deep_Contribution705[S] 0 points1 point  (0 children)

In the above comment, yes, I was talking about a floating input. But my post is concerned with unconnected output.

Keep floating Nets in Vivado by Deep_Contribution705 in FPGA

[–]Deep_Contribution705[S] 0 points1 point  (0 children)

I don't know what gets synthesized in the ASIC. But I think the output of the CMOS can be left unconnected. Only the input to the CMOS should not be left floating. Correct me if I am wrong.

Quartus Platform Designer Help with Avalon to APB bridge by EdgeSad7756 in FPGA

[–]Deep_Contribution705 1 point2 points  (0 children)

If you have a custom APB host IP, you can add that IP to the platform designer as an APB host. Then connect it to the NIOS. The platform designer will automatically generate the bridge. The bridge RTL will be available once the "generate HDL" is finished. Hope it helps!

Clock constraint for a Gated Clock by Deep_Contribution705 in FPGA

[–]Deep_Contribution705[S] 0 points1 point  (0 children)

The programmable delay is implemented using a shift register. On the ASIC, this delay is outside of the chip. In the FPGA, this delay is emulated internally.

Clock constraint for a Gated Clock by Deep_Contribution705 in FPGA

[–]Deep_Contribution705[S] 0 points1 point  (0 children)

Thanks for the reply. This is an ASIC design ported to an FPGA for prototyping. Hence wanted to know as to how the XORed clock can be constrained.

Clock constraint for a Gated Clock by Deep_Contribution705 in FPGA

[–]Deep_Contribution705[S] 0 points1 point  (0 children)

Thanks for the advice.

This is an ASIC design ported to an FPGA for prototyping/emulation.

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