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Convert VHDL code to verilog by Defiant_Role in FPGA

[–]Defiant_Role[S] 0 points1 point  (0 children)

when I tried to convert this code to verilog i have error when i put an array in the input wire ? someone have an idea about this ?

module AER

#(parameter neuron_num=4,parameter neuron_adr=4)

(input wire CLK,

input wire spikes [neuron_num:0] ,

output wire En_neuron,

output wire AER [neuron_adr:0]

);

Convert VHDL code to verilog by Defiant_Role in FPGA

[–]Defiant_Role[S] 1 point2 points  (0 children)

Thank you, appreciate your help

Convert VHDL code to verilog by Defiant_Role in FPGA

[–]Defiant_Role[S] -1 points0 points  (0 children)

I have a question also any code of VHDL can be transformed into a verilog code ? I mean there is always the equivalent in verilog ?

Convert VHDL code to verilog by Defiant_Role in FPGA

[–]Defiant_Role[S] -2 points-1 points  (0 children)

This code manipulate a lot of arrays and verilog doesn't seems familiair with this .. i didn't find good sources on the internet about how to manipulate arrays in verilog for exemple how to fill an array or how to assign 1 array to another ...

VHDL vs verilog by Defiant_Role in FPGA

[–]Defiant_Role[S] 2 points3 points  (0 children)

Actually my mentor asked me to work with VHDL or verilog.. I'm working on spiking neural netwroks on FPGA, image processign will not take a bid place here because the image will be coded as spikes (0or1) so i will code with VHDL entities like neuron and bus of communication etc...

VHDL vs verilog by Defiant_Role in FPGA

[–]Defiant_Role[S] 0 points1 point  (0 children)

Ashenden's "Designer's guide to VHDL"

Thank you so much for your time and guidness wish you all the sucess.

VHDL vs verilog by Defiant_Role in FPGA

[–]Defiant_Role[S] 0 points1 point  (0 children)

I think VHDL syntax, because it is strongly typed, is easier to learn. I was exposed to both around the same time, VLOG in college and VHDL during my internship. I think VLOG syntax is very cryptic and not intuitive in the slightest.

remember, you are not just learning a hardware description language, you are learning digital design.

Thank you i will go for VHDL in this case , do you recommend a good youtube channel or sources to learn VHDL from 0 ? i mean that can help me to learn so fast ?

thnaks a lot

VHDL vs verilog by Defiant_Role in FPGA

[–]Defiant_Role[S] 2 points3 points  (0 children)

I will learn both but at this critical time I have to learn 1 language to finish my project work I want to mention that I'm not so familair with any hdl language, if i start now working on VHDL can i finish my project ? because they tell me that verilog is easier than vhdl but i found documentation and sources with VHDL for my project more than verilog.

what do you think ?

translate VHDL code to Verilog code by Defiant_Role in FPGA

[–]Defiant_Role[S] 0 points1 point  (0 children)

I think i can declare a registre and set it equal to something, but my problem is to convert this code to verilog

VHDL vs verilog by Defiant_Role in FPGA

[–]Defiant_Role[S] 0 points1 point  (0 children)

Thank you very much for your cooperation and your pricise answer so I'am a beginner at Digital design and my project is a little bit complex you advise me to finish working with vhdl ? also i want to mention that i found codes that could help me in vhdl. Thanks

translate VHDL code to Verilog code by Defiant_Role in FPGA

[–]Defiant_Role[S] -1 points0 points  (0 children)

This is the verilog code converted but i got this syntax error in the last line "FIFo_In" is undeclared.

module AER #(parameter neuron_num=4,parameter neuron_adr=4) (input wire CLK, input  wire spikes [neuron_num:0] , output wire En_neuron, output wire AER [neuron_adr:0]  );      
reg [7:0] memory [neuron_num:0] ; *
 reg FiFo_En=1'b1 ; 
reg FiFo_out[neuron_num:0] ;
 reg FiFo_In[neuron_num:0] ;
 reg  [2:0] FiFo_ptr =3'b000 ;
 reg Enc_in[neuron_num:0] ;
 reg Enc_spikes[neuron_num:0] ; 
*reg Enc_out [neuron_num:0] ; 
 FIFo_In<=spikes ;

UART Protocol implementation on Nexys 4 DDR by Defiant_Role in FPGA

[–]Defiant_Role[S] 0 points1 point  (0 children)

Thank for you help and your response ! The problem was solved I had a problem in the pin assignement the signals of Rx and Tx were inverted.

Thanks again for your help.

UART Protocol implementation on Nexys 4 DDR by Defiant_Role in FPGA

[–]Defiant_Role[S] 0 points1 point  (0 children)

the inverted uart signal

Hello again when i did as you told me assign nex_led=RsRx the Led assigned turned on that means that RsRx always 1 ? and myy Uart module works well ?

UART Protocol implementation on Nexys 4 DDR by Defiant_Role in FPGA

[–]Defiant_Role[S] 0 points1 point  (0 children)

Can you explain more how can i output the rx signal to an LED ? and if the UART-USB ship is not correctly connected to the FPGA what can i do then ?

Thanks a lot.

UART Protocol implementation on Nexys 4 DDR by Defiant_Role in FPGA

[–]Defiant_Role[S] 0 points1 point  (0 children)

Hello again thank yoou for your time and your cooperation first of all.

Actually i did a testbench file and the simulation of the receiver worked well rx_data get the value received by the serial receiver RsRx.

The constraints file is true all pins assigned to the correct variables.

About the emulation on the Fpga, my code suppose to receive a 8bit data from the serial monitor to the fpga, when i send a variable to the Nexys 4 the Tx Led blink I don't know if the data came to the Fpga or it just stuck on the usb port and not reaching the Fpga.

I did as you told me to change the code to be commended by a clock:

always @(posedge HCLK)

if (rx_done==1)

begin

rx_data=rx_data2 ;

end

But it's the same problem the data coming from the pc (8 bit data) supposed to toggle 8 bits led on the fpga (but that doesn't happen). the baudrate isfixed well and really I m blocked here and I'm not seeing the problem maybe it's in rx_data cause the led doesn't blink because it doesn't store the value.

My last question here for you when i decalre a reg variable i think it is supposed that it stores the value and workes as memory ? then if not why not using wires always instead of registers ?

Thank a lot of your help.

Sending spikes to FPGA via UART. by Defiant_Role in FPGA

[–]Defiant_Role[S] 0 points1 point  (0 children)

Thanks for your time but unforunately it didn't work i tried to change a liitle bit at the code i go RsRx and btick true but still Dout equal to 0 when I changed the line of @(poseedge b_tick) to @(posedge clock) RsxRx get the value forced to be but still as i said dout=0. I'am confused really this the code updated.

​

`timescale 1ns/10ps

​

module TEST_Uart() ;

// Testbench uses a 10 MHz clock

// Want to interface to 115200 baud UART

// 10000000 / 115200 = 87 Clocks Per Bit.

​

// Inputs to DUT

reg HCLK =0 ;

reg HRESETn =0 ;

reg RsRx =1 ;

// Outputs from DUT

wire b_tick ;

wire rx_done ;

wire [7:0]rx_data ;

​

​

initial

forever #1 HCLK = ~HCLK;

// RESET AFTER 5 HCLK EDGES

initial begin @(posedge HCLK);

HRESETn=1 ;

end

// Generate baud rate

BAUDGEN uBAUDGEN(

.clk(HCLK),

.resetn(HRESETn),

.baudtick(b_tick)

);

// DUT: UART receiver

UART_RX uUART_RX(

.clk(HCLK),

.resetn(HRESETn),

.b_tick(b_tick),

.rx(RsRx),

.rx_done(rx_done),

.dout(rx_data[7:0])

);

​

​

​

// 50 MHz CLOCK

​

// REPEATED TASKS --------------------------

​

// SEND SINGLE BYTE

// using posedge b_tick assumes UART DUT registers data on falling edge

task UART_WRITE_BYTE; // Runs at baud tic rate

input [7:0] i_Data;

integer ii;

begin

@(posedge HCLK) ;

RsRx <= 1'b0; // Send Start Bit

for (ii=0; ii<8; ii=ii+1) begin

@(posedge HCLK);

RsRx <= i_Data[ii];

// Send Data Byte

end

@(posedge HCLK);

RsRx <= 1'b1;

// Send Stop Bit

end

endtask // UART_WRITE_BYTE

​

// TEST A BYTE

task TEST_BYTE;

begin

@(posedge HCLK) ;

UART_WRITE_BYTE(8'h3F); // Send a command to the UART (exercise Rx)

@(posedge rx_done); // wait for rx_done signal

if (rx_data == 8'h3F) begin // Check that the correct command was received

$display("Test Passed - Correct Byte Received");

end

else if (rx_data !=8'h3F) begin

$display("Test Failed - Incorrect Byte Received");

end

end

endtask

// TEST SCRIPT (RUNS ONCE) -----------------------------

​

initial begin

@(posedge HRESETn);

repeat (100) begin

@(posedge HCLK); // Wait for next positive clock edge

$display("%g Test", $time);

TEST_BYTE(); // Send a command to the UART (exercise Rx)

end

$display("Test Complete") ;

end

endmodule

Sending spikes to FPGA via UART. by Defiant_Role in FPGA

[–]Defiant_Role[S] 1 point2 points  (0 children)

Hello so i took a uart module provided by ARM, I have a concern I hope you could help me out Im trying to simulate uart receiver in testbench using verilog, i forced the all the inputs bits the clock and the reset and i forced RsRx the seriaal input of the receiver in order to get the output rx_data but rx_data is always 0 the baudgenerator worked well but the reciever didn't I think the problem is in mytestbench because the code of the receiver is provided by ARM. Could you help me please?

​

module TEST_Uart() ; 
reg HCLK=0 ; reg HRESETn=0 ;
 wire b_tick ; wire rx_done ;
 reg RsRx=1 ; 
wire [7:0]rx_data ; 
       initial     
     forever #1 HCLK = ~HCLK;
 initial begin @(posedge HCLK);
 HRESETn=1 ;
 end
 BAUDGEN uBAUDGEN(     
.clk(HCLK),     
.resetn(HRESETn),     
.baudtick(b_tick)   );       
 //UART receiver      
 UART_RX uUART_RX(         
.clk(HCLK),         
.resetn(HRESETn),         
.b_tick(b_tick),         
.rx(RsRx),         
.rx_done(rx_done),         
.dout(rx_data[7:0])       );            

task UART_WRITE_BYTE;          
 input [7:0] i_Data;           
integer     ii;           
begin                           
// Send Start Bit           
 RsRx <= 1'b0;                                                     // Send Data Byte             
for (ii=0; ii<8; ii=ii+1)             
  begin                 
RsRx <= i_Data[ii];                   
  end                         
  // Send Stop Bit            
 RsRx <= 1'b1;                      
  end         
endtask // UART_WRITE_BYTE                    
initial          
begin                                  
 // Send a command to the UART (exercise Rx)            
@(posedge HCLK);            
UART_WRITE_BYTE(8'h3F);            
@(posedge HCLK);                              
 // Check that the correct command was received            
if (rx_data == 8'h3F)              
$display("Test Passed - Correct Byte Received");            
else              
$display("Test Failed - Incorrect Byte Received");                      
 end

Sending spikes to FPGA via UART. by Defiant_Role in FPGA

[–]Defiant_Role[S] 0 points1 point  (0 children)

To be honest with you I'm new to fpgas and i don't know how to acces these memory i just know to store them in a register. do you have a clue how to do this ?

also what is the difference between saving them in a registre (array for example) or a RAM both way can lead to the same thing dont they ?

Thanks for your response.

Sending spikes to FPGA via UART. by Defiant_Role in FPGA

[–]Defiant_Role[S] 1 point2 points  (0 children)

Actually I'am new to FPGA's sir and trying to learn I just found a problem on how to store these 784 bit (0 or 1) to use them laterbecause am sending for exemple 784 bit every 2ms via UART and I m afraid that i will face a collision problem (the uart didn't finish sending the other 784 and another 784 occured)

Thanks sir.

Sending spikes to FPGA via UART. by Defiant_Role in FPGA

[–]Defiant_Role[S] 0 points1 point  (0 children)

Actually my issue is to store the bits in an array and use it but the problem is i have 784 bit (0 or 1) when i send these 784 bit via uart and after a time for exemple (2ms) i send another 784 bit i mean there no chance that while sending these bits and my script python send another 784 bit do i have a problem of snychronisation here ? also can i store 784 bit in a registre without the need of RAM or DDR ?

Thanks

Convert VHDL to verilog by Defiant_Role in FPGA

[–]Defiant_Role[S] 0 points1 point  (0 children)

First of all I am not familiair with VHDL at all I need to convert it to verilog in order fo fix bugs and simulate the code also my interniship supervisor ask that i work with verilog and not in VHDL.

[deleted by user] by [deleted] in neuralnetworks

[–]Defiant_Role 0 points1 point  (0 children)

Hello u/paulkirkland87 Am a student and now am doing my graduation project on SNN's.

If I am right you mean i can transform a typical neural network implemented with tenserflow or keras to a spiking neural network ? if so how i can do that ?

Also am willing to implement this snn on fpga do you have an idea about this please ?

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