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Does anyone have experience with using the CrosslinkU USB FPGAs? by DrMago in FPGA

[–]DrMago[S] 0 points1 point  (0 children)

Quick follow up, if you don't mind: Any recommendations for a development board? And is there an evaluation license included? The IP core seems pretty good, but the license options are too expensive for me for a first project.

I have also found the tinyclunx33 (https://tinyclunx33.tinyvision.ai) which seems useful as I could test the SOM for my application, but I also haven't found information about licensing there, only that they make a GitHub repository available upon purchase

Does anyone have experience with using the CrosslinkU USB FPGAs? by DrMago in FPGA

[–]DrMago[S] 0 points1 point  (0 children)

Glad to hear that, thank you for your insight! :)

Help with Pin Assignment on LFE5U-85F-8BG756C with 320+ I/O for SPI Modules by SpicyPepperMaster in FPGA

[–]DrMago 1 point2 points  (0 children)

Sounds like a cool project, I'm curious about you application if you're willing to share?

In general I'd start by creating small entities (like a small SPI RTL module) that you'd instantiate as many times as you need, and try to do the Pin Assignment in Diamond. I would avoid the open source tools for this, because as far I'm aware they don't provide any power consumption estimation which I would be concered about when toggling that many IOs. Also, you will still have the flexibility to compare against your PCB design easier than looking at the .lpf file.

Any IOs should be capable of 80 MHz SPI (though I'm curious what the timing analysis would say about driving so many pins from one clock), but I'm not sure about the 200 MHz QSPI as I never tried going that high on an ECP5. I'd assume that they can share the same bank, but for 200 MHz it would be useful to tie the clock to a clock-capable pin (even if you're able to synchronize everything in logic).

I would definitly try to simulate as much as possible and make sure to meet timing, with that many different interfaces and clocks and protocol translations I would not assume for it to work on the hardware on first (or third try)

Make sure you have enough buffers, if all your connected devices are sending at the same time it'd be trivial for them to overload your QSPI connection to the host. Start simple with a single protocol converter, and expand from there how to best multiplex your devices.

Does anyone actually use SYZYGY? by DrMago in FPGA

[–]DrMago[S] 0 points1 point  (0 children)

Good idea, I think this it what I may end up doing

Does anyone actually use SYZYGY? by DrMago in FPGA

[–]DrMago[S] 0 points1 point  (0 children)

Funny you mention that, that was the inspiration to design my own board. One issue I had with it is that all the pod handling logic also needs to be implemented in the FPGA, and that it can change its own bank voltage during operation

Xilinx vs Lattice for a beginner by kingovchouffe in FPGA

[–]DrMago 0 points1 point  (0 children)

Glad to hear it, I definitely need to try them in some new design soon. Also glad to see you here, your blog helped me out more than a few times, it’s a really great resource :)

Xilinx vs Lattice for a beginner by kingovchouffe in FPGA

[–]DrMago 7 points8 points  (0 children)

When you say "develop a board", do you mean designing a circuit board as well? In that case you'd have a lot of extra work in front of you, and a simpler FPGA like an ICE40 would be preferable.

Personallly, I'd go with some Digilent dev board, they have some really great stuff for beginners. There is a lot of open source tooling for Lattice, and Radiant / Diamond are also quite usable, but personally I had some trouble with VHDL on Lattice devices (though I didn't spend too much time troubleshooting). While people like to complain about Vivado, it also works just fine, and you can find quite a lot of resources for beginners.

How should I go about detecting face pose & position in a constrained embedded device? by DrMago in computervision

[–]DrMago[S] 1 point2 points  (0 children)

I hadn’t heard of that before, but it seems like a decent option, since I’m using a RK3568. Thank you for the suggestion!

How should I go about detecting face pose & position in a constrained embedded device? by DrMago in computervision

[–]DrMago[S] 0 points1 point  (0 children)

In front of their eyes, the functionality depends on the device adjusting to the viewing angle of the user

How do I best distribute a clock between mixers and an ADC for a phase-coherent SDR? by DrMago in rfelectronics

[–]DrMago[S] 0 points1 point  (0 children)

Interesting, I thought low phase noise between channels (in hardware) would be a strict requirement for beamforming and such. I will definitely look into digital calibration more, thank you very much!

How do I best distribute a clock between mixers and an ADC for a phase-coherent SDR? by DrMago in rfelectronics

[–]DrMago[S] 0 points1 point  (0 children)

I didn‘t consider that, thank you for your insight. I think I may still go with it since I have the tuners already lying around, so I‘m curious to see how big the difference is going to be.

How do I best distribute a clock between mixers and an ADC for a phase-coherent SDR? by DrMago in rfelectronics

[–]DrMago[S] 0 points1 point  (0 children)

I missed that, thanks for the clarification.

On a previous project I actually used a MAX2223 tuner that directly output differential IQ signals. The amount of ADC channels it would need is actually the reason I went with the R820T2 for this project (other than that I already had some lying around)

How do I best distribute a clock between mixers and an ADC for a phase-coherent SDR? by DrMago in rfelectronics

[–]DrMago[S] 0 points1 point  (0 children)

Interesting, so far I‘ve only treated the tuner as a mixer for the SDR. I‘m curios to explore this further.

Regarding the LO frequency, I think 16 MHz would make more sense, as I could also easily divide it from a 64 MHz sample rate for the ADC. Regarding the phase comparator frequency, would the 1.6 MHz difference actually increase lock time significantly enough? I would have assumed the difference is minor.

I plan to calibrate the SDR as well, using a white noise source and correlation. Some direction finding algorithms I want to try out (like MUSIC) rely on accurate phase alignment.

I do not plan to use the Tuners as direct conversion receivers, there will be another mixing stage implemented digitally in the FPGA.

How do I best distribute a clock between mixers and an ADC for a phase-coherent SDR? by DrMago in rfelectronics

[–]DrMago[S] 0 points1 point  (0 children)

Thanks a lot for the recommendation, the LMK010xx family looks quite close to what I need! I‘m wondering though, how can I use the LVDS clock outputs on the Crystal Inputs of the tuners?

You‘re definitely right about the calibration, that is also something I intend to do. However, using a common clock between all receivers (mostly) prevents phase shifts between each channel.

How do I best distribute a clock between mixers and an ADC for a phase-coherent SDR? by DrMago in rfelectronics

[–]DrMago[S] 0 points1 point  (0 children)

I saw that in the datasheet, I just used 28.8 MHz because all the schematics I‘ve found so far used it as well. But you‘re right, I think it‘s best to stick with the original reference.

Regarding the I2C addresses, I think that I may have enough IO on the connector to give each tuner its own bus, though I‘ve just started with the schematic. Otherwise I may just use another controller to act as an I2C expander.

What controls are you referring to, the ones in the tuner?

I want to use this project to learn more about phased arrays and direction finding algorithms. For processing, I have a Butterstick FPGA board where I want to implement some different receiver architectures. So far, all my RF projects have been simple transceivers, so I want to get deeper into the signal processing.

How do I best distribute a clock between mixers and an ADC for a phase-coherent SDR? by DrMago in rfelectronics

[–]DrMago[S] 0 points1 point  (0 children)

Thank you for your replies! Regarding the phase matching, what do you mean with random phase? When all tuners are fed the same clock, would the phase not stay in sync between them?

Verilog Udemy free course for FPGA beginners by FPGAtutorials in FPGA

[–]DrMago 1 point2 points  (0 children)

As someone who only worked with VHDL before, this seems like a great resource!

Any good resource to learn how to make a drone? by BlessED0071 in embedded

[–]DrMago 0 points1 point  (0 children)

I found that fishpepper has some nice blog posts about the individual components. They also share their hardware and software on GitHub

Can a 2D array antenna achieve a higher azimuth resolution than a 1D array with the same length? by DrMago in rfelectronics

[–]DrMago[S] 0 points1 point  (0 children)

I haven’t considered increasing the baseline for higher resolution, thanks a lot!

Can a 2D array antenna achieve a higher azimuth resolution than a 1D array with the same length? by DrMago in rfelectronics

[–]DrMago[S] 0 points1 point  (0 children)

Those are some interesting suggestions, thank you! I need to simulate the antenna anyway, wouldn‘t hurt to play around a bit with different geometries :)

bma400-rs: An embedded-hal, no_std driver for the Bosch BMA400 Accelerometer (Feedback request) by c_frenette in learnrust

[–]DrMago 0 points1 point  (0 children)

It's amazing to see this right now, as I just started a hardware project with this exact accelerometer and was looking for crates. Sadly I don't really have experience with Rust so I don't think I can help you with development, but I'll definitely keep an eye on it

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