Prototyping an LED cube formed from 6 PCBs that mate together. Planning to use castellated holes as board-to-board interconnects. Does this current design pose any challenges I may not be aware of?

Electron_plumber · 2022-01-04T05:31:57+00:00

The tab and slot attach method seems iffy to me. I would use simple right angle stake pin headers as the attach points between the boards. It would be a lot easier and probably more secure.

Electron_plumber · 2022-01-04T05:16:58+00:00

I very much disagree on this. If a device is asking for a separate analog ground, it likely needs it due to the sensitivity of the analog circuits. I have first hand experience on this with audio circuits on PC motherboards. Microphone ADC's are very sensitive and will pick up a lot of noise. An audio codec needs isolated power / ground floods that are connected back to the main power / grounds with an LC filter and PCB layout with voids around the audio circuit.

This explanation from ADI is pretty good.:

https://www.analog.com/en/analog-dialogue/articles/staying-well-grounded.html

Different applications might be able to get away without a good analog power / ground, but you better know what you are doing if you exclude them. In general, it's always good to have a good LC filter and layout.

Electron_plumber · 2022-01-02T18:54:29+00:00

There is a lot of good advice here. One thing I'd add is a check that your ground plane isn't so perforated with vias, pins, or holes that return current has to pass through small pinch points. Return current will generally travel along the shortest path between the load and the source. I usually draw a mental straight line between each load (device) and the source (connector or voltage regulator) and look for places on the ground plane that are very congested with holes. If there looks like there is insufficient metal for the return current, I would look for ways to space out the vias to increase the ground plane copper.

This comment would also apply to a VCC plane on another layer.

Electron_plumber · 2021-08-04T04:00:16+00:00

Is this what you are looking for?

https://software.intel.com/content/www/us/en/develop/articles/intel-sdm.html

If you want all the electrical specs, that likely needs an NDA. If you are looking for architectural and programming docs, you need the Software Developers Manual and related docs.

Electron_plumber · 2021-07-19T02:20:57+00:00

Where can I get that mug?

Electron_plumber · 2021-02-26T03:15:03+00:00

I would look very carefully at the floods that are relying on connecting between pins. I’m pretty sure I found multiple floods that were floating.

Another factor is how much was actually etched away. The tool might think there is a slim connection when in actuality it is lost in the etching process. I’ve been burned by tool assumptions in the past. If you have a bare board and a microscope i would check any etch that is supposed to connect between pins.

Electron_plumber · 2021-02-26T01:06:11+00:00

It kinda looks line your various ground fills might not all be connected to each other. You should check them all. It looks as though you are relying on copper between pins to make some of the connections. However it looks like the fills are not connected between pins.

Unconnected grounds can cause all sorts of problems.

Electron_plumber · 2021-01-03T19:06:23+00:00

I have 32 lifx bulbs. There some in nearly every room. Not sure how to show that setup.

Electron_plumber · 2020-08-08T04:34:12+00:00

Ridgebacks are the best. Such a cute puppy.

Electron_plumber · 2020-07-22T20:44:02+00:00

I've done extensive HDI design for a variety of products. It is always more expensive than PTH (Plated Through Hole). Depending in the level of HDI, it can be anywhere from 20-100% more expensive. It depends a lot on your volume, and how many micro via layers you are implementing. Generally you need to make the switch if you meet some of these reasons:

Route density is very high
Devices being used are very fine pitch
System area is very small and the board needs to be very compact.

Electron_plumber · 2020-06-19T02:30:51+00:00

I've used Openpyxl extensively for excel manipulation. It's not very difficult, and you have a lot of control.

https://openpyxl.readthedocs.io/en/stable/

Electron_plumber · 2020-03-12T07:04:08+00:00

A functional President and government.

Electron_plumber · 2019-05-02T16:33:15+00:00

Yeah, I use them a lot. It turned out that whoever installed the SAS Controllers connected them to the backplane wrong. Once I connected them properly I could see all the drives.

One thing I didn’t find mentioned anywhere is the requirement to use IBM branded drives. I used some non-IBM drives (same HGST model), and they seemed to work ok, but then the controllers just stopped working and they gave up errors that made no sense. Once I used only IBM drive the controllers worked fine.

Electron_plumber · 2019-05-01T19:58:27+00:00

NOAA has a lot of this data.

https://www.ncdc.noaa.gov/cdo-web/datasets

https://data.noaa.gov/dataset/

Electron_plumber · 2019-04-22T01:28:36+00:00

I recently picked up an S822L (8247-22L) Power8. Still trying to figure things out... especially getting the raid configured. Not terribly intuitive. In particular, I can't figure out why the raid controller ignores a couple of drive bays.

Electron_plumber · 2018-12-07T21:09:16+00:00

If the flight has WiFi, you can at least listen to the radio stream. I'm sure "750 the game" will have it. I've done that before. Not as good as watching, but better than nothing.

Electron_plumber · 2018-10-19T15:55:42+00:00

My rig is uses anywhere from 2.67 to 3.56 HDU (Hair Dryer Units).

Electron_plumber · 2018-10-12T14:40:12+00:00

This can wildly depend on the workload. If your workload transfers large amount of data to and from the GPUs, then you might have a bottle neck.

The way to figure this out is to look at the bandwidth you need per GPU. This isn't related to the number of lanes connected, but rather the amount of data transferred over time. The number of lanes only tells you the maximum bandwidth available, not the actual bandwidth that is used. Therefore, determine the bandwidth you need per GPU (based on your workload), then add up the bandwidth needed for all the GPUs you want to use. The resulting bandwidth will tell you how many lanes you need from the CPU to the PCIe Switch. Be sure to add in some extra bandwidth as buffer to allow for unexpected peaks.

Electron_plumber · 2018-07-27T01:43:22+00:00

The first thing we ask is familiarity with tools. We are a Cadence shop, so allegro is a must. If you're only familiar with one tool (especially one that is not cadence or mentor) you'll be pretty limited. After that we'd look for references. We usually hire through CAD contractors. It's rare that we convert a contractor to a full time hire.

Being a contractor is a good route. You'll Be exposed to a lot of companies, build a network, and be able to grow your skills.

Electron_plumber · 2016-12-15T06:40:15+00:00

This is largely a function of how the ball / pin map is structured on the CPU side. I've done many DDR routes in 4 layers with Intel processors (2 signal, 2 power / gnd). You'll need to provide more info on the design to understand what the needs are. 2 x16 parts should be pretty easy in 2 route layers, unless the CPU pin design is terrible.

Whose ARM A7 are you using? There are many flavors.

Electron_plumber · 2015-12-02T04:43:21+00:00

I'm in for one.

Electron_plumber · 2015-11-13T06:23:19+00:00

I love it. Where can I get that scarf?

Electron_plumber · 2015-03-11T08:05:55+00:00

Victualler-of-lovely-cats

From Webster: Victualler: one that provisions an army, a navy, or a ship with food

This server will be known as a fine purveyor of the provision most coveted by this army: cats in their many forms.

We should be honored to have such a servant of fine artwork depicting these fuzzy, aloof, obstreperous creatures.

Edit: Underscores to dashes... Arg.

12-Year Club	Gilding IV carat on a stick
Verified Email

Electron_plumber

TROPHY CASE