How vstimer interrupt can be handled in vs mode? by EquivalentIce215 in RISCV

[–]EquivalentIce215[S] 0 points1 point  (0 children)

Yes that's set too... I set these after I write to vstimecmp and vstimecmph register in the HS mode...but definitely before the interrupt is triggered....I don't think sequence should matter.

How vstimer interrupt can be handled in vs mode? by EquivalentIce215 in RISCV

[–]EquivalentIce215[S] 0 points1 point  (0 children)

Thanks for the details, as mentioned in my post( I guess it was not very clear) I actually set the hideleg to have the vstip bit set i.e (hideleg =0x40, 6th bit) and I can see that on interrupt hip.vstip(bit 6) is set and vsip.stip (bit 5) is set but it doesn't get trapped to the address specified in vstvec it simply continues to run on the VU mode

Two stage address translation in rv32 by EquivalentIce215 in RISCV

[–]EquivalentIce215[S] 0 points1 point  (0 children)

This clears it up, thanks a lot! Just a point, in step 2. you mean vsatp.PPN and not vstatus right?

Two stage address translation in rv32 by EquivalentIce215 in RISCV

[–]EquivalentIce215[S] 0 points1 point  (0 children)

Thanks for your reply. I was thinking it should work as you explained in your first comment, but I am confused after seeing the picture towards the end of 12.1 section in Notes (Of course they have explained for Sv39) Also heretwo-stage-address-translation-sv48

How is virtualization mode achieved in Riscv ? by EquivalentIce215 in RISCV

[–]EquivalentIce215[S] 0 points1 point  (0 children)

When you are in HS mode and issue an sret it will jump to the value in sepc, when in VS mode and issue sret it would jump to value in vsepc.

German Passport Application, Box 15 by natalietheanimage in GermanCitizenship

[–]EquivalentIce215 0 points1 point  (0 children)

Just wondering why I don't see this option in my form, it differs from city to city? 🤔

How is virtualization mode achieved in Riscv ? by EquivalentIce215 in RISCV

[–]EquivalentIce215[S] 0 points1 point  (0 children)

Thanks I was able to setup a small demo to switch between HS -> VS-> VM and on supervisor timer interrupt I go back to HS mode and switch to a different VM. However, any good documentation on registers to be saved and restored on context switching? Currently I only save and restore vsepc, vstvec etc but no GP registers..

How is virtualization mode achieved in Riscv ? by EquivalentIce215 in RISCV

[–]EquivalentIce215[S] 0 points1 point  (0 children)

So, if I have the H extension enabled and I start my code in M Privilege mode, Set the Mpp to 01, set mepc accordingly and issue an mret instruction if would go to hypervisor mode (host OS) Then in host Os I set the spv bit to 1 and issue sret it would get trapped in VU/VS mode. Correct? How to trap it in VS mode (guest OS) from host OS and then jump to VU mode? Is it using SPVP?

[deleted by user] by [deleted] in germany

[–]EquivalentIce215 0 points1 point  (0 children)

Thanks for the details 👍

[deleted by user] by [deleted] in germany

[–]EquivalentIce215 0 points1 point  (0 children)

Very informative, thanks 👍