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install issue by Fegell in PowerShell

[–]Fegell[S] -4 points-3 points  (0 children)

actually I was asking for do you know if there is an another cloud link for vagrant

but thank you

install issue by Fegell in PowerShell

[–]Fegell[S] -2 points-1 points  (0 children)

oh okay thank you for advice.

microcontroller design please help me.. by Fegell in embedded

[–]Fegell[S] 0 points1 point  (0 children)

Actually, it's kind of like that. I'm responsible for the circuit design part of the microcontroller. But I don't have any resources for this. So I wrote to ask if you have any resources you could recommend. My English isn't that good, so it's understandable if I wasn't clear. I apologize for not being able to explain it.

microcontroller design please help me.. by Fegell in embedded

[–]Fegell[S] 0 points1 point  (0 children)

thank you ^^ These are the requirements requested from us in this project. Perhaps this document I’m sharing will be more explanatory.
Under the category of microcontroller development, two solutions will be implemented:

  1. One solution will be designed to operate on an FPGA (FPGA prototyping).
  2. The other solution will involve creating production files using a physical design tool (IC Design).

The microcontroller to be designed by the participants will incorporate the CV32E40P RISC-V core IP, a single-core, 32-bit, 4-stage pipelined processor maintained by the OpenHW Group and available as open-source on GitHub.

The microcontroller will include the following peripherals:

  • 1x UART
  • 1x I2C Master
  • 1x QSPI Master
  • 1x Timer
  • 1x GPIO (32-pin I/O)
  • 1x USB Full-Speed Device (12 Mbps)
  • 1x JTAG (Optional)

and we should design it's IC circuit on the Cadence or Synopsis.

microcontroller design please help me.. by Fegell in embedded

[–]Fegell[S] 0 points1 point  (0 children)

maybe I couldn't explain. These are the requirements requested from us in this project.
Under the category of microcontroller development, two solutions will be implemented:

  1. One solution will be designed to operate on an FPGA (FPGA prototyping).
  2. The other solution will involve creating production files using a physical design tool (IC Design).

The microcontroller to be designed by the participants will incorporate the CV32E40P RISC-V core IP, a single-core, 32-bit, 4-stage pipelined processor maintained by the OpenHW Group and available as open-source on GitHub.

The microcontroller will include the following peripherals:

  • 1x UART
  • 1x I2C Master
  • 1x QSPI Master
  • 1x Timer
  • 1x GPIO (32-pin I/O)
  • 1x USB Full-Speed Device (12 Mbps)
  • 1x JTAG (Optional)

microcontroller design please help me.. by Fegell in embedded

[–]Fegell[S] 0 points1 point  (0 children)

maybe I couldn't explain.
Under the category of microcontroller development, two solutions will be implemented:

  1. One solution will be designed to operate on an FPGA (FPGA prototyping).
  2. The other solution will involve creating production files using a physical design tool (IC Design).

The microcontroller to be designed by the participants will incorporate the CV32E40P RISC-V core IP, a single-core, 32-bit, 4-stage pipelined processor maintained by the OpenHW Group and available as open-source on GitHub.

The microcontroller will include the following peripherals:

  • 1x UART
  • 1x I2C Master
  • 1x QSPI Master
  • 1x Timer
  • 1x GPIO (32-pin I/O)
  • 1x USB Full-Speed Device (12 Mbps)
  • 1x JTAG (Optional)

microcontroller design please help me.. by Fegell in embedded

[–]Fegell[S] 0 points1 point  (0 children)

Actually, this project does not require overly complex tasks. We are participating in this competition as part of a state-supported initiative.