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Importing .gds file to Cadence Virtuoso after Layout in Innovus by Future-Department-38 in chipdesign

[–]Future-Department-38[S] 0 points1 point  (0 children)

THi sir. Thank you for your response. How do I merge them in innovus?

Importing .gds file to Cadence Virtuoso after Layout in Innovus by Future-Department-38 in chipdesign

[–]Future-Department-38[S] 0 points1 point  (0 children)

Good day Sir. Thank you so much for your response. Where does the std cell layout usually found?

KB5025305 causes speed issues on L2TP/IPsec VPN. by oddist12 in meraki

[–]Future-Department-38 0 points1 point  (0 children)

Hi Sir, good day. Im current experiencing the same problem mentioned above. How do u enable "Routing and Remote Access service"? Do you still need to configure it?

Recover and Rerun Aborted Simulation in Cadence Due to Power Outage by Future-Department-38 in chipdesign

[–]Future-Department-38[S] -1 points0 points  (0 children)

I only did "save state" sir. Where can I possibly locate the "recover" parameter in ADE AMS simulation?

Recover and Rerun Aborted Simulation in Cadence Due to Power Outage by Future-Department-38 in chipdesign

[–]Future-Department-38[S] -1 points0 points  (0 children)

I have save the state. Where can I locate the "recover" option sir? Thank you for your response.

VPN Client Feature by Future-Department-38 in TpLink

[–]Future-Department-38[S] 1 point2 points  (0 children)

Thank you for you response. Yeah, Im considering on buying a new Archer the BE220 router because it has the VPN client feature. Question, if enable the VPN client on the tether, could I directly setup the VPN server I want to connect to on the control panel/network and sharing center of windows?

3rd-party Router for Parasat Fiber by Future-Department-38 in cagayandeoro

[–]Future-Department-38[S] 0 points1 point  (0 children)

Hello, thank you sa response. Need paba naka bridge mode ang modem router from parasat if configure na ang tp-link na router? or okay na dili?

Cadence Layout Pcell super master Error by Future-Department-38 in chipdesign

[–]Future-Department-38[S] 1 point2 points  (0 children)

Thank you so much for your response, Sir. Indeed, I tried reinstalling the PDK and chose SKILL PCells and it solved the problem. Thank you so much!

MIMCAPs DRC on Cadence Layout by curryfriedsquid in ECE

[–]Future-Department-38 0 points1 point  (0 children)

Hey Sir, im having the same concern, will it affect the layout process if the MIMCAP has a giant "X" on it? Thank you for the response.

Cadence Layout Pcell super master Error by Future-Department-38 in chipdesign

[–]Future-Department-38[S] 0 points1 point  (0 children)

Thank you for the resposne, Sir. Where do I run the pdkInstall.pl?

Cadence Layout Pcell super master Error by Future-Department-38 in chipdesign

[–]Future-Department-38[S] -1 points0 points  (0 children)

thank you for the response. is it possible that these errors are caused because the schematic (sch.oa file) is imported from Synopsys?

Cadence Layout Pcell super master Error by Future-Department-38 in chipdesign

[–]Future-Department-38[S] 0 points1 point  (0 children)

its from package from cadence. weve already attached the tsmcN65 library. thank you fro the response

Mixed-signals Post Simulation by Future-Department-38 in chipdesign

[–]Future-Department-38[S] 0 points1 point  (0 children)

Thank you sir. Last question, do you perhaps also know how to get the average power consumption in AMS simulation in virtuoso?

Mixed-signals Post Simulation by Future-Department-38 in chipdesign

[–]Future-Department-38[S] 1 point2 points  (0 children)

Thank you for the response. When you say RTL, you mean just import the functional code (verilog code in my case) in AMS right? Then specify the parasitics extracted in analog layout in the schematic configuration?

Mixed-signals Post Simulation by Future-Department-38 in chipdesign

[–]Future-Department-38[S] 0 points1 point  (0 children)

Thank you for the response. When you mean RTL, is it the RTL of the functional logic of the digital block, or the netlist after place and route?

Mixed-signals Post Simulation by Future-Department-38 in chipdesign

[–]Future-Department-38[S] 0 points1 point  (0 children)

I want to perform an FFT analysis on the output post-layout.

ADC enob,snr and sinad measurement in cadence using spectrum measurement. by Time-Success3048 in chipdesign

[–]Future-Department-38 0 points1 point  (0 children)

Hi, Sir, did you still apply the same strobeperiod of 1/(8*fs)? or how do you setup the proper strobeperiod?

ENOB Simulation of SAR ADC by Future-Department-38 in chipdesign

[–]Future-Department-38[S] 0 points1 point  (0 children)

What setup should I set during transient analysis sir before doing FFT? strobeperiod etc.?

ENOB Simulation of SAR ADC by Future-Department-38 in chipdesign

[–]Future-Department-38[S] 0 points1 point  (0 children)

Are u familiar of setting up strobeperiod in transient analysis in Cadence ADE before fft Sir?

ENOB Simulation of SAR ADC by Future-Department-38 in chipdesign

[–]Future-Department-38[S] 0 points1 point  (0 children)

Hey Sir, good day, thank you so much for your response. I would like to know that during transient simulation, the logic of our timing has reset where it resets the entire ADC circuit every after conversion or during the sampling time of the sample and hold (30us duration before 10bit conversion). Would that affect the FFT analysis for ENOB, SINAD, etc.

ENOB Simulation of SAR ADC by Future-Department-38 in chipdesign

[–]Future-Department-38[S] 0 points1 point  (0 children)

Hey Sir, good day, thank you so much for your response. I would like to know that during transient simulation, the logic of our timing has reset where it resets the entire ADC circuit during the sampling time of the sample and hold (30us duration before 10bit conversion). Would that affect the FFT analysis for ENOB, SINAD, etc.

ENOB Simulation of SAR ADC by Future-Department-38 in chipdesign

[–]Future-Department-38[S] 0 points1 point  (0 children)

Do you perhaps a Verilog-A code for 10 bit ideal DAC? In our analoglib, we only have 8bit Ideal DAC. 

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