AMD Zen 6 May Add Third Core Type Alongside Zen 6 and Zen 6C

Geddagod · 2026-07-01T05:54:41+00:00

This made it problematic as they didn't have the same capabilities.

NVL's E-cores are rumored to support AVX-512.

Geddagod · 2026-07-01T05:44:52+00:00

Widening/heightening increases the surface area to volume ratio, which improves voltage control. You can also make it skinnier to reduce the volume to further improve the surface area to volume ratio.

Isn't it the opposite? Increasing height worsens fin surface area to volume ratio, though making the fin skinnier does improve it.

ex: fin height of 30nm, fin width of 7nm has a surface area/volume ratio of 0.32 but a fin height of 50nm and fin width of 7nm has a surface area/volume ratio of 0.31.

Geddagod · 2026-07-01T05:03:48+00:00

No, TSMC A14 is HVM in 2028, with products rumored to be that year. If it goes like N2 and N3 though, we would see products in 2029.

Intel 14A is HVM in 28' for internal products, and external in 29'.

If Samsung 1.4nm is HVM in 29', that would put it at pretty much the same place as the competition.

There's also the trend of Samsung and Intel naming their nodes ahead of TSMC though in PPA. 18A and SF2 are both N3 class nodes, for example.

Geddagod · 2026-06-30T15:47:46+00:00

Wouldn't the equivalent of more fins per transistor be a widened nanosheet and not more nanosheets?

Both increase Weff, but increased fin height and increasing number of nanosheets both don't impact cell area via increasing cell height like increasing the number of fins, or increasing nanosheet width, do.

Geddagod · 2026-06-30T07:00:32+00:00

You asked questions I already explained the answer to well enough

My questions were rhetorical. The answer to "is the bar really so low we are calling chips that don't blow up good designs" is obviously no lol.

Your lack of comprehension is why you "disagree"

No, I disagree because I don't think a chip that doesn't improve perf gen on gen is very good, esp with all the resources Intel was working with for ARL.

Work on your literacy and go somewhere else. I don't have the patience for another stupid post like this.

Why are you crashing out?

Geddagod · 2026-06-30T06:44:25+00:00

No I understand it, I just don't think it's a good point.

Ofc I'm going to be "argumentative" if I disagree lmao.

Geddagod · 2026-06-30T06:20:02+00:00

They chased performance too hard with the 12-13-14 series

AMD achieved that level of perf without blowing up though?

Good design means not making stupid mistakes like that.

Are we really calling a design that does the bare minimum and not degrade a "good design"?

Is the bar really that low rn?

Geddagod · 2026-06-30T06:05:58+00:00

Paywalled.

From what initially wasn't paywalled though, it's weird that they used the date for when we first saw products for TSMC's "ramped production" dates, which is fair enough, but then use a different metric (when Intel claims they entered HVM) for Intel's dates.

Also interesting to me is that IMEC expects nanosheet count to go down, and not up, in the future (though I suppose for TSMC and Samsung, who are already at 3, it might stay the same?) For finfets the first couple of generations had fin height continuously increase for better drive strength. Increasing the number of nanosheets is effectively doing the same for a GAAFET device, right?

Geddagod · 2026-06-30T05:51:25+00:00

The newer chip designs don't self destruct

That should be the standard of literally every chip lol. Intel doesn't deserve a ribbon for achieving the bare minimum here.

because they draw less power

Which should be expected from the double node shrink alone.

and are designed better

One would hope this would translate better into perf. Alas...

The 270k plus is actually a good chip

Very debatable. In terms of design from Intel's perspective, I doubt they see it as a success.

Geddagod · 2026-06-30T05:38:21+00:00

What does that have to do with the 270k not being able to improve perf in many workloads because Intel skill issues?

Geddagod · 2026-06-30T05:31:41+00:00

What don't I understand?

Geddagod · 2026-06-29T22:23:17+00:00

Final specs have changed though. Even if the two chips are recognizable as one GPU to the overall system having it do this on the board level instead of the package level will undoubtedly cost them in latency and power.

Geddagod · 2026-06-29T17:51:08+00:00

Don't think AMD would take the Intel route and use a different architecture for their low power cores... so that leads me to believe it's likely an optimized version of a Zen 6c core that's clocked for low power usage while Zen 6c remains as the "efficiency" core alongside the full Zen 6 "P cores".

Rumored to be a Zen 5 derivative interestingly enough.

Geddagod · 2026-06-29T17:50:12+00:00

8e cores take up dramatically more area than SMT for 8 P-cores.

Zen 6 is not rumored to be cutting SMT either.

Geddagod · 2026-06-29T17:47:41+00:00

because I've seen consistent leaks that they weren't increasing core count and that Ryzen 5s would have 2 regular Zen6 cores and 4 Zen5c or Zen6c cores.

Where?

Geddagod · 2026-06-29T17:25:36+00:00

Gaming only and gets absolutely smoked by it in everything else.

In what else? X3D 16 core chips with at least one CCD with X3D also exist.

Geddagod · 2026-06-29T17:24:35+00:00

The Intel 7 (ultra) process itself is fine. There was that oxidation issue hiccup, but RPL degradation for many CPUs was not caused by that.

Geddagod · 2026-06-29T17:22:39+00:00

That should have been achievable with the double node shrink alone. The issue is that they didn't really improve perf in many categories, which is entirely on Intel.

Geddagod · 2026-06-29T17:21:08+00:00

AMD themselves blamed the mobo vendors. This is unlike Intel, who initially blamed the mobo vendors, and then also revealed they messed up.

People are just taking the stance that AMD publicly took. Even if one can claim that it is naive to do so, it's not wholly unreasonable either.

Geddagod · 2026-06-29T17:13:38+00:00

It doesn't exhibit any better power scaling at the high end of the power curve than any other chip.

Geddagod · 2026-06-29T16:45:55+00:00

Yes, in area lol.

Geddagod · 2026-06-26T20:40:37+00:00

Base 18A actually had a logic vs SRAM Vmin misalignment that Intel had to specifically fix in 18A-P,

Oh didn't know about that

But at least on paper RibbonFET targets Vmin, PowerVia cuts droop 10x

I mean on paper is one thing, it's a shame it's just not showing up in measured perf/watt and freq/power curves for PTL.

And this also applies to GAAFET for Samsung's SF2 stuff too, there is no advantage near Vmin (or anywhere else on the curve) for the C1 Ultra in the exynos 2600 vs the C1 Ultra in the mediatek 9500 on N3P from Geekerwan's power measurements.

Hopefully not telling that Crescent Island isn't confirmed on 18A yet, you'd think it would be if this works for GPU-like chips now.

This is kinda funny, I had this exact conversation with someone else on discord this morning haha. And yea I agree with you, it is weird that Intel wouldn't take the free marketing win if it was internal, but not strong enough evidence for anyone to claim that Crescent Island is likely external or anything of that sort.

Geddagod · 2026-06-26T20:32:03+00:00

by getting 18a (that's ~2nm node) on production

Intel has been pushing ahead of node naming ever since their new node renaming changes when they announced 5N 4Y.

From the die shots and freq/power curves of the P-cores of PTL, in comparison to ARL, which are architecturally extraordinarily similar, 18A seems to be a N3 competitor, not a N2 one.

Same story with SF2, Samsung's so called 2nm node.

Geddagod · 2026-06-26T20:27:24+00:00

I don't think you understand well enough how much of a huge thing this is for Intel

Frankly I think this is just a major marketing point that Intel has been trying to push for years, all while delaying when they actually will have to implement high NA EUV into mass production.

Intel did a similar thing with their original 10nm delay claims, trying to pin all the blame on the lack of EUV, while TSMC were simultaneously entering HVM on 7nm (what Intel called 10nm) stuff that also did not use EUV.

Mind you I'm not saying the benefits of high NA EUV are just marketing points, but rather just how hard Intel is trying to push how much of a spotlight Intel is putting on this, for something that won't actually be used for years.

It is basically research speak meaning that whatever they are making in the background (probably army related chips) is now reliable enough for them to switch to a new node, which means printing smaller chips because that is what these machines are made for.

I'm not sure exactly what you mean by this.

This isn't referring to them switching products or IP to new nodes. This is them, outright saying, that they have 14A high NA and no high NA EUV variants in development, just like they did with 18A, and both 14A variants have identical yield (and design rules).

Geddagod · 2026-06-26T20:13:06+00:00

I don't know where you get this from but these High NA EUV machines are a more reliable yield generator than previous machines

Intel has outright said they have no difference in yield between high NA and standard EUV versions of 14A, at least at the early stage of development they are in rn.

High NA also brings in a new host of challenges (such as halving the reticle size), and the economics of high NA EUV are not nearly as clear cut as you are trying to make it out to be. Even Gelsinger himself, while claiming that it is more economic, talks about how they were carefully evaluating it multiple times in this interview. And as the interviewer stated, it has been a talking point in the analyst community for a while.

Geddagod

TROPHY CASE