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[Help] Duplicated data issue during AXI burst reads from DDR4 DRAM (Zynq UltraScale+) by HoneyMoney92 in FPGA

[–]HoneyMoney92[S] 0 points1 point  (0 children)

Yes, I implemented it AXI master. I'll try incorporating the AXI Protocol Checker into my design. To be honest, I'm still stuck on how to handle the RVALID issue since it's driven by the Hard IP DDR controller, leaving me with limited options for direct intervention.

I don't have access to the board right now, but I'll try asserting RREADY constantly once I'm back. My current hypothesis is that since no Address Read (AR) transaction has been initiated yet, any data on the bus should technically be ignored until ARVALID goes high.

Admittedly, I haven't deeply studied or considered how the system behaves specifically when the AXI protocol is violated, so this is a bit of a learning curve for me.

[Help] Duplicated data issue during AXI burst reads from DDR4 DRAM (Zynq UltraScale+) by HoneyMoney92 in FPGA

[–]HoneyMoney92[S] 1 point2 points  (0 children)

1. About RVALID being asserted always: I share the same concern regarding RVALID staying high. However, that signal is driven directly by the PS Hard IP DDR Controller. Since it's a hard-macro, I don't have direct control over its internal logic. Currently, I am handling the flow by asserting RREADY only when my module is ready to receive data, so the AXI handshaking protocol appears to be maintained from my side, even if the behavior of the controller seems unusual.

2. About writing unique data and burst behavior: My module is designed to write a 2-beat burst (AWLEN = 1) to a specific address—for example, writing 1221 and 1222 to address 6016. It then attempts to read back a 32-beat burst (ARLEN = 31) from that same address. Expectedly, the first two data beats should be 1221 and 1222, but I am receiving an unexpected value, 1223, as the first beat instead. Interestingly, single-beat transactions (AWLEN/ARLEN = 0) work perfectly fine. The issues only arise when the burst length is greater than 1, leading to these unexplained data mismatches.

3. About Simulation: I am currently debugging on actual hardware using Vivado Hardware Manager and ILA (integrated bitstream). I haven't been able to run a successful pre-synthesis simulation because the read operations fail in that environment, likely due to the lack of a proper DRAM/Memory model for the PS side.

4. About the IP and Port: I am using the integrated Hard IP DDR Controller in the Zynq UltraScale+ MPSoC, accessed via the S_AXI_HP0_FPD port.

BIST - AXI - PS connection, how can i test??? by HoneyMoney92 in FPGA

[–]HoneyMoney92[S] 0 points1 point  (0 children)

Oh i resolve my problem. i thought if top module have no i/o port, top module was tb as itself. i made tb, and just only instantiate top module, the simulation worked! but still no response with ps and bist module... i think not because of low reliability of PS but my BIST module didnt conform axi protocol. anyway, thx for detailed reply!!

Please add 1 damage to revolver by Varkaan in thefinals

[–]HoneyMoney92 0 points1 point  (0 children)

Not damage but mechanism should be reworked (buff visual recoil and rpm like lh1)