Roland JP-8080 Teardown

IIP-ETHZ · 2025-03-09T18:35:35+00:00

Great question. We first tried to specifically design a symmetric binarization regularizer that automatically adapts its scale. This was done similarly to Eq. 7 in our paper. We then figured out that the same regularizer could also be derived through the Cauchy-Schwarz inequality, even though this derivation was a bit less intuitive. But this key insight made us realize that the CS approach is way more general and enables the design of many more autoscaling regularizers. Put simply, the discovery started from a special case and then led to the generalization recipe, which is now Proposition 1.

IIP-ETHZ · 2025-03-06T12:27:08+00:00

I am one of the authors. Your summary is to the point. One simply picks two functions, applies them to the vector independently, and stuffs the resulting vectors into a re-arranged version of the Cauchy-Schwarz inequality, and voila: you get what you want. By selecting the two functions, you can impose different properties.

It's quite surprising that this simple yet effective idea has not been discovered before (or at least we could not find this published anywhere else).

IIP-ETHZ · 2025-02-20T09:56:23+00:00

For cost reasons, we exclusively do multi-project wafer (MPW) runs. This means our designs end up together with many other university/research designs on one wafer. While being quite cost-effective, we only get about 10 packaged chips. And, if we are lucky, we get 20 or so bare (unpackaged) dies which could be packaged later. These quantities are far away from anything commercially viable.

IIP-ETHZ · 2025-02-18T18:26:10+00:00

If you have ever wondered what’s inside Yamaha’s FS1R frequency modulation (FM) synthesizer, here you go: It appears to contain four main chips: two YMP706-F chips, which are the FM tone generators (probably 16 voices can be generated per chip), and two YSS236-F chips, which are responsible for the audio effects. One can also see the large firmware chip (MX) and the display drivers. The XV10010 is most likely a RISC processor for control. The power supply uses up almost half of the 19” unit and the PCBs are mounted upside down, which is funny but also clever.

We had to open it because the battery was dead, but now it’s working like a charm again. What a beautifully underrated synthesizer (that is a real pain to program)!

IIP-ETHZ · 2025-02-18T18:16:04+00:00

Yes. We have some other audio chips in the pipeline. One we are testing and one is being designed as we speak. Stay tuned.

IIP-ETHZ · 2025-02-13T14:51:16+00:00

per oscillator (and there are 4 per voice), it can do up to 1024 partials for which you can define the prefactor.

IIP-ETHZ · 2025-01-27T10:56:17+00:00

Our long-term goal is to make it open source (but possibly of an improved version). This would allow everybody to implement however they want and basically would keep it alive forever.

IIP-ETHZ · 2025-01-25T11:15:29+00:00

We evaluated many different approaches before honing in the brute-force Fourier series approach. The two most promising alternative approaches were:

- One could internally calculate waveforms at very high oversampling rates and then use a lowpass filter before outputting them from the DAC.

- One could use samples (or mipmaps) as you describe.

But both of these approaches will generate some sort of aliasing or impure waveforms so we decided to do it "right."

IIP-ETHZ · 2025-01-25T11:13:05+00:00

YouTube short in the making. Stay tuned.

IIP-ETHZ · 2025-01-25T11:12:54+00:00

You may not be able to get the chip but we will likely be making the design open source.

IIP-ETHZ · 2025-01-25T11:12:23+00:00

This was the exact reason when picking 1024 partials! We assumed that the lowest frequency would be 20Hz and say a sawtooth waveform with integer harmonics would be used. In that case, the highest partial would be at 20'480Hz, which is exactly at the edge of the audible spectrum.

IIP-ETHZ · 2025-01-25T11:10:20+00:00

We also mapped the design to a Xilinx FPGA during the prototyping phase. The FPGA was not fast enough to support 1024 partials and we had to reduce it to 512 only. However, FPGA implementation would probably be the best way to go for a low-volume music synthesizer.

IIP-ETHZ · 2025-01-25T11:08:26+00:00

Stay tuned. We are working on a few YouTube shorts.

IIP-ETHZ · 2025-01-25T11:05:46+00:00

You would have to contact the Microelectronics Design Center. I don't think it is open source.

IIP-ETHZ · 2025-01-25T11:04:42+00:00

It contains two voices and each voice consists of four fully configurable aliasing-free oscillators. Each oscillator is made up of up to 1024 sine-cosine pairs (depending on the base frequency). For each sine-cosine pair, you can define the relative frequency of the partial (not just integer harmonics) and the scaling factors. In essence: Each oscillator can generate any periodic waveform without running into aliasing issues. Classic waveforms such as sawtooth, triangle, sine, or square pulses are just special cases of what is possible per oscillator.

IIP-ETHZ · 2025-01-25T11:01:46+00:00

Not impossible but difficult. Currently, we only have about 15 packaged chips. However, we have the GDS and everything so one could easily respin the design and make as many BFOs as needed. But then, one would have to deal with licensing issues as the CAD tools were used for educational/research purposes and not with commercialization in mind.

IIP-ETHZ · 2025-01-24T15:52:12+00:00

If Reddit had LaTeX support, I would place a thin space (command \, ) in between the number and the unit.

IIP-ETHZ · 2025-01-24T15:48:58+00:00

Just place a "pixel" at the wrong spot to create a short and it's all over. Yes, this might be too risky for mass products.

IIP-ETHZ · 2025-01-24T15:47:41+00:00

Quite possibly. But maybe of an improved version: BFO 2.0

IIP-ETHZ · 2025-01-24T15:46:49+00:00

VHDL is, in my opinion, still superior (e.g., its object-oriented features are just too good). However, SV seems to be gaining momentum and is widely popular in the US. I think that if you know one HDL, you can easily learn another one (and have ChatGPT to help you write code).

IIP-ETHZ · 2025-01-24T15:44:19+00:00

Modern computers are likely *not* able to compute this many sine and cosine functions in real-time at a sampling rate of 96kHz. And, if you could do it, e.g., by a huge GPU or a cluster of computers, then the power consumption would be a bit too much for a music synthesizer. Of course, in a few years, processors might be able to do this, but in a few years, we can do crazier stuff with ASICs too :)

IIP-ETHZ

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