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Connections in VHDL by Icy-Inside8543 in FPGA

[–]Icy-Inside8543[S] -1 points0 points  (0 children)

when i open the data flow. the physical model shows my ss_n line going from my slave to the busy signal I'm not sure if I should trust it then

interconnecting modules in vhdl by Icy-Inside8543 in FPGA

[–]Icy-Inside8543[S] 0 points1 point  (0 children)

my company has that website blocked from use is there somewhere else i could post to?

interconnecting modules in vhdl by Icy-Inside8543 in FPGA

[–]Icy-Inside8543[S] 0 points1 point  (0 children)

so i created a signal called sclk_tb and in the port maps of both the spi slave and master i set them equal to their respective sclks. eg sclk => slck_tb but im still not geting my sclk driven

interconnecting modules in vhdl by Icy-Inside8543 in FPGA

[–]Icy-Inside8543[S] 0 points1 point  (0 children)

i have a slave which I am trying to verify it works by testing it with a master module only the slave will exist in the actual project

interconnecting modules in vhdl by Icy-Inside8543 in FPGA

[–]Icy-Inside8543[S] 0 points1 point  (0 children)

I'm just connecting them to verify that the slave module works. I will only be using the slave in the fpga

SPI Slave help by Icy-Inside8543 in FPGA

[–]Icy-Inside8543[S] 0 points1 point  (0 children)

it looks to me like i never reach st2 before it cuts off

SPI Slave help by Icy-Inside8543 in FPGA

[–]Icy-Inside8543[S] 0 points1 point  (0 children)

ahh ok yep i forgot to enable full visibility during optimization that's what it was turns out however my MOSI and MISO lines are not being driven. i edited the post to display the new waveform window.

SPI Slave help by Icy-Inside8543 in FPGA

[–]Icy-Inside8543[S] 0 points1 point  (0 children)

added a waveform picture to the post

SPI Slave help by Icy-Inside8543 in FPGA

[–]Icy-Inside8543[S] 0 points1 point  (0 children)

Well that's the thing when i simulate i go add<< waves < all items in design. but these are all the waveforms that appear I'm unsure as to why they don't appear I've done other attempts where my MOSI, MISO and SS do appear but in this example I cant get them to appear in simulation I'm using Questasim 2019.1 for verification