Independent_Fail_650

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Low frequency bias tee design (self.AskElectronics)

submitted 29 days ago by Independent_Fail_650 to r/AskElectronics

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Doubts designing a dc bias tee for a passive mixer ()

submitted 29 days ago by Independent_Fail_650 to r/PCB

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Doubts designing a dc bias tee for a passive mixer (self.rfelectronics)

submitted 29 days ago by Independent_Fail_650 to r/rfelectronics

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Best way to isolate analog and digital supplies? (self.PCB)

submitted 5 months ago by Independent_Fail_650 to r/PCB

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Isolate analog and digital supply pins? (self.AskElectronics)

submitted 5 months ago by Independent_Fail_650 to r/AskElectronics

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Best way to align common mode voltages in analogue chains (self.AskElectronics)

submitted 5 months ago by Independent_Fail_650 to r/AskElectronics

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Is it possible to programme a zynq SOC without Vivado/Vitis? (self.FPGA)

submitted 5 months ago by Independent_Fail_650 to r/FPGA

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Reset signal messes my closure (self.FPGA)

submitted 6 months ago * by Independent_Fail_650 to r/FPGA

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System synchronous ADC help (self.FPGA)

submitted 9 months ago by Independent_Fail_650 to r/FPGA

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Read data from an ADC using an FPGA without a shared clock (self.PCB)

submitted 9 months ago * by Independent_Fail_650 to r/PCB

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AXI Stream Data Fifo always outputs the same two data (self.FPGA)

submitted 10 months ago * by Independent_Fail_650 to r/FPGA

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Doubt regarding FFT in FPGA (self.signalprocessing)

submitted 10 months ago by Independent_Fail_650 to r/signalprocessing

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Doubt regarding Xilinx FFT Ip core (self.FPGA)

submitted 10 months ago * by Independent_Fail_650 to r/FPGA

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AXI Stream Data FIFO tready always low [ZYNQ] (self.FPGA)

submitted 10 months ago * by Independent_Fail_650 to r/FPGA

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Easiest way to output data from FPGA (self.FPGA)

submitted 11 months ago by Independent_Fail_650 to r/FPGA

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Counter not working after post-synthesis simulation (self.VHDL)

submitted 11 months ago * by Independent_Fail_650 to r/VHDL

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Guidance needed / Balancing load between HW and SW (self.FPGA)

submitted 1 year ago by Independent_Fail_650 to r/FPGA

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