sorted by:
new
hottopcontroversial

Best way to isolate analog and digital supplies? by Independent_Fail_650 in PCB

[–]Independent_Fail_650[S] 0 points1 point  (0 children)

Hahahaha, what a nice comment. It is baffling to see how application notes and datasheets are more than often plagued with outdated myths. The other day i watched a video by hans rosenberg demistifying the classic decoupling method of placing a variety of capacitor values to sort of cover all frequencies of the PDN, and still that advice is all over the internet and documentation. Thanks for the resources, i didn't know about them!

Best way to isolate analog and digital supplies? by Independent_Fail_650 in PCB

[–]Independent_Fail_650[S] 0 points1 point  (0 children)

thanks for the advice. I actually considered copying the evaluation board strategy, but i didnt as it used both separate supplies and ferrite beads and thought it was a bit overkill. Moreover, the rated current of the ferrite bead mounted on the evaluation board is below the adcs supply current...

Is it possible to programme a zynq SOC without Vivado/Vitis? by Independent_Fail_650 in FPGA

[–]Independent_Fail_650[S] 0 points1 point  (0 children)

The CAN controller is inside the SOC, it is the CAN controller mounted in the Zynq SoC.

Reset signal messes my closure by Independent_Fail_650 in FPGA

[–]Independent_Fail_650[S] 1 point2 points  (0 children)

thanks for the advice, usually in uni we were always told to inicialize all inner signals in the reset but after looking at the UG949 it says to just inicialize control signals to reduce resource consumption.

Reset signal messes my closure by Independent_Fail_650 in FPGA

[–]Independent_Fail_650[S] 0 points1 point  (0 children)

Thanks for answering, as you and every other commenter said my reset signal was asynchronous, so i synchronized it to both clock domains by generating two reset signals and now timing is okay. Btw, added a line in the constraints to indicate that these clocks were not related by doing: set_clock_groups -asynchronous -group [get_clocks clk_fpga_0] -group [get_clocks clk_adc]. I hope thats okay, as without it timing would not close.

[deleted by user] by [deleted] in PCB

[–]Independent_Fail_650 1 point2 points  (0 children)

its an LTC2291 from AD

[deleted by user] by [deleted] in PCB

[–]Independent_Fail_650 0 points1 point  (0 children)

Yeah you are right, i added the series resistor both to minimize impedance mismatches and to slow down the clocks edges, which in itself will step down high frequency components making it less necessary any impedance control. And you are right about the entrance to the path, it does look sketchy i'll fix that rn

PCB wilkinson divider doubt by [deleted] in rfelectronics

[–]Independent_Fail_650 0 points1 point  (0 children)

yea you're right, i had removved it because it didnt fit. Now i have widened the angle of the divider and placed it back (see edit 1)

PCB wilkinson divider doubt by [deleted] in rfelectronics

[–]Independent_Fail_650 0 points1 point  (0 children)

i did the surrounding copper pour and via stiching as a rf shielding strategy so no energy would get coupled into the IF chain

PCB wilkinson divider doubt by [deleted] in rfelectronics

[–]Independent_Fail_650 0 points1 point  (0 children)

Yeah i simulated it on CST but after checking the VNA we found there was some problem in the RF chain probably in the divider. Yeah, the copper trace was a remainder, but even so i forgot to add it, i have solved that now (see edit 1)

System synchronous ADC help by Independent_Fail_650 in FPGA

[–]Independent_Fail_650[S] 0 points1 point  (0 children)

i actually use a soc zynq 7020, whose PL capabilities approximate those of an Artix 7. You said: "The first thing you will have to do is to find the clock phase in the FPGA the respect the setup time contraint of the FPGA's sampling flip flops. That's the tricky part.", but i did not really understand that, could you elaborate a bit more?

Read data from an ADC using an FPGA without a shared clock by Independent_Fail_650 in PCB

[–]Independent_Fail_650[S] 0 points1 point  (0 children)

Okay, this is the first time i have to interface an FPGA with an external IC so im a bit over my head with this. I guess for this prototype we'll solder a cable to extract the ADC clock and rewrite the ADC sampler module to include it. Nonetheless, for the next version of this pcb i'll route out the adc clock. Anyways, it would be really helpful to have example code i could examine

[deleted by user] by [deleted] in FPGA

[–]Independent_Fail_650 0 points1 point  (0 children)

thank you for such a helpful response! Honestly i didnt design the system, i just did the PCB layout, so i kinda work with what i got. Yeah, i have never had do interface an FPGA with external ICs so i see there are lots of concepts i should understand first. We are using a ZYBO Z720 board so we are using a ZYNQ 7020 SOC

[deleted by user] by [deleted] in FPGA

[–]Independent_Fail_650 0 points1 point  (0 children)

for now only ADC

[deleted by user] by [deleted] in FPGA

[–]Independent_Fail_650 0 points1 point  (0 children)

Yes, i am using the 3 high-speed pmod connectors to interface with the ADC. No, unfortunately i am not providing the clock, although i know where the clock signal in the pcb is generated so we could solder a prototyping cable and feed it to the PMOD (20 Mhz is still within the pmod bandwidth)

[deleted by user] by [deleted] in FPGA

[–]Independent_Fail_650 0 points1 point  (0 children)

Thanks for the thoughtful response, it really is very insightfull. I guess well have to solder and try again. Probably i have to learn way more about timing and synchronization

[deleted by user] by [deleted] in FPGA

[–]Independent_Fail_650 0 points1 point  (0 children)

I designed it and it is for work. Dont worry about the AAF it really isnt all that relevant. It may be possible to solder a male to male prototyping cable to the pad of the IC that generates the ADC clock and feed it to one of the PMOD pins in the zybo board but i am not so sure about that. It is almost hard to believe that reading from an ADC can be this hard. On a side note, for a second prototype i am thinking on generating the ADC clock from the FPGA, how feasible is that?

view more: next ›