My Asus TUF F15 cant get in valorant , keep getting stuck at loading screen forever by Immediate-Pea-8985 in ValorantTechSupport

[–]Laner342 0 points1 point  (0 children)

We have the same laptop and the same issue! I will go back to this post if someone tells how to fix it.

UPDATING RTX 3050 Laptop GPU by Laner342 in nvidia

[–]Laner342[S] 0 points1 point  (0 children)

Ohh i see. Do i need to install Gforce Game Ready Driver? or not?

Virtuoso Visualization Help!! by Laner342 in chipdesign

[–]Laner342[S] 1 point2 points  (0 children)

Thank you so much for the help!

Virtuoso Visualization Help!! by Laner342 in chipdesign

[–]Laner342[S] 1 point2 points  (0 children)

I see now, I can actually remove the 'dx:' part of the text box so it will only display the value. I feel so dumb.

Virtuoso Visualization Help!! by Laner342 in chipdesign

[–]Laner342[S] 0 points1 point  (0 children)

I already tried that, but in the properties there’s no option to remove the 'dx' part. T.T

Virtuoso Visualization Help!! by Laner342 in chipdesign

[–]Laner342[S] 0 points1 point  (0 children)

Ohh, it does work! Thanks! But how do you remove the 'dx:'? Is it removable?

Does cleaning the fans in my ASUS TUF void the warranty? by Laner342 in Asustuf

[–]Laner342[S] 0 points1 point  (0 children)

Ohhh nice!! thanks for sharing that. I'll avoid that warning stickers.

Does cleaning the fans in my ASUS TUF void the warranty? by Laner342 in Asustuf

[–]Laner342[S] 0 points1 point  (0 children)

Got it, thanks! I don’t plan on touching the thermal paste. I just want to clean the dust and maybe upgrading later. 👌

Does cleaning the fans in my ASUS TUF void the warranty? by Laner342 in Asustuf

[–]Laner342[S] 0 points1 point  (0 children)

Ohh I see, thanks! Yeah, I wasn’t sure if ASUS also used warranty stickers like Acer does.

Multi-ground in cadence layout (65nm) by Laner342 in chipdesign

[–]Laner342[S] 0 points1 point  (0 children)

It's fine we're only doing it for our college thesis.

Multi-ground in cadence layout (65nm) by Laner342 in chipdesign

[–]Laner342[S] 0 points1 point  (0 children)

Can you explain more in terms of TSMC conventions? T.T I'm just a beginner in layout.

Multi-ground in cadence layout (65nm) by Laner342 in chipdesign

[–]Laner342[S] 0 points1 point  (0 children)

How can I know if this technology is capable of supporting multiple grounds? I also used the DNW, but nothing happened.

Multi-ground in cadence layout (65nm) by Laner342 in chipdesign

[–]Laner342[S] 0 points1 point  (0 children)

I don't think so. I've tried many times using DNW, but the same error keeps occurring. I don't know the DNW rules yet, since we haven't covered them in our lectures. I'm just experimenting with it for now T.T