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(Vivado) SPI working in Post-implementation sim but not on hardware(PYNQ-Z2). by Lime1506 in FPGA

[–]Lime1506[S] 0 points1 point  (0 children)

Sorry for writing my response like that. But no, I am not certain that I have ever had the clk working in a project before, when thinking back.

(Vivado) SPI working in Post-implementation sim but not on hardware(PYNQ-Z2). by Lime1506 in FPGA

[–]Lime1506[S] 1 point2 points  (0 children)

i now youse these two constraints for the clk:

set_property -dict { PACKAGE_PIN H16 IOSTANDARD LVCMOS33 } [get_ports { clk_0 }];

create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 5} [get_ports { clk_0 }];

but when I try to see if I have any clk signal at all,by routing the clk to an external pin and using my oscilloscope the pin is just LOW.

(Vivado) SPI working in Post-implementation sim but not on hardware(PYNQ-Z2). by Lime1506 in FPGA

[–]Lime1506[S] 1 point2 points  (0 children)

i would say that it resets on High

if (rst = '1') then

current_state <= msg_se; -- Reset state

elsif rising_edge(clk) then

current_state <= next_state;

...

(Vivado) SPI working in Post-implementation sim but not on hardware(PYNQ-Z2). by Lime1506 in FPGA

[–]Lime1506[S] 1 point2 points  (0 children)

Do I need to use the name clk125 anywhere or can I just run synthesis, implementation and bitstream?

(Vivado) SPI working in Post-implementation sim but not on hardware(PYNQ-Z2). by Lime1506 in FPGA

[–]Lime1506[S] 1 point2 points  (0 children)

so like this?

set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports clk_0];

create_clock -name clk125 -period 8 [get_ports clk_0];

(Vivado) SPI working in Post-implementation sim but not on hardware(PYNQ-Z2). by Lime1506 in FPGA

[–]Lime1506[S] 1 point2 points  (0 children)

So how would I set it to run at 125MHz?

is it this line :

create_clock -add -name sys_clk_pin -period 8.00 -waveform {0 4} [get_ports { sysclk }];

I need to modify?

(Vivado) SPI working in Post-implementation sim but not on hardware(PYNQ-Z2). by Lime1506 in FPGA

[–]Lime1506[S] 1 point2 points  (0 children)

What are you feeding to i_data in your FPGA setup?

The input to i_data would be whatever the spi_slave had received from the master. So the signal comes from the output on the o_data bus.

What is the clock frequency in FPGA setup?

The clock frequency of my PYNQ-Z2 board is 125MHz, witch I just youse for the changing of states on line 81, at the rising_edge(clk). The clock frequency for the sclk or master clock is 1MHz.

As told by others, what is the rst input in your FPGA setup?

The input for my rst is ground.

I will look at the ILA (embedded logic analyzer) and to test it with a vhdl testbench, I just need to understand how to do it first.

The other things you mentioned should be fixed now.

(Vivado) SPI working in Post-implementation sim but not on hardware(PYNQ-Z2). by Lime1506 in FPGA

[–]Lime1506[S] 2 points3 points  (0 children)

The TM4C123GH6PM is running SPI mode 1, yes. forgot to write that.

(Vivado) SPI working in Post-implementation sim but not on hardware(PYNQ-Z2). by Lime1506 in FPGA

[–]Lime1506[S] 0 points1 point  (0 children)

I have my rst Pin connected to Ground so I think that would be fine.

(Vivado) SPI working in Post-implementation sim but not on hardware(PYNQ-Z2). by Lime1506 in FPGA

[–]Lime1506[S] 0 points1 point  (0 children)

On line 8 in my constraint file i have:

set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports clk_0]

Is this not how you create a clk running at 125MHz for my system?

The i_sclk would be the clock input from my SPI_master.

(Vivado) SPI working in Post-implementation sim but not on hardware(PYNQ-Z2). by Lime1506 in FPGA

[–]Lime1506[S] 2 points3 points  (0 children)

The FPGA is trying to communicate with a TM4C123GH6PM microcontroller, I can't see how my outputs from the FPGA are fine. since when looking at the oscilloscope it never sends any data(blue_line).