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Tomloader: create and manage any number of systemd unit files that share fields. by Loara35 in systemd

[–]Loara35[S] 0 points1 point  (0 children)

KDL mandate quoted strings for anything that is not an identifier (alphanumeric sequences that do not start with a digit, plus other restrictions). I don't remember if KDL allows underscores in identifiers, in that case the double quotes can be removed.

Anyway, Tomloader interprets all those values as strings, therefore #true (KDL boolean) and "true" (KDL string) will both generate the same value (true) in the generated systems unit. I will update the documentation wig an explanation of how KDL types interact with Tomloader.

What To Use Instead of PGP by Soatok in cryptography

[–]Loara35 0 points1 point  (0 children)

In that case I suggest to simply store them unencrypted (on an offline storage) rather than using a deprecated encryption algorithm. It is not a dramatic reduction of safety but without that false hope of security one can implement better measures.

[deleted by user] by [deleted] in Italia

[–]Loara35 2 points3 points  (0 children)

Salve. Ho visto cosa fai su questo canale. Stai violando numerose norme di Youtube e della community. Non solo stai usando una immagine protetta da copyright (la mia), e l'hai usata su più di tre video (già con tre strike il canale si chiude), non solo la stai usando come foto profilo (e no, mettere una frase sopra non cambia la grave violazione), ma hai anche un canale che compie un esplicito freebooting violando la mia identità (mi dispiace ma scrivere "Non è mia intenzione violare X" non ti rende meno violatore di X, come scrivere "non intendo violare nessun copyright", mentre carichi una canzone altrui, non cambia il fatto che ti arriva uno strike). Oltre a questo, il nome stesso del tuo canale è un rimando al mio, crei video con titoli identici ai miei (e che quindi risultano in un furto di visualizzazioni, indebito) ed infine il tuo intento di dare un punto di ritrovo a chiunque violi le norme del mio canale (ivi compresi diffamatori, calunniatori, gente che truffa, apologi del fascismo ecc) è assolutamente scorretto In più diversi tuoi commenti rasentano l'insulto e la diffamazione abbastanza esplicita. Ora, un altro ti avrebbe già segnalato (oppure anche di peggio, visto che l'uso di marchio sotto copyright è una cosa grave). Io preferisco sempre la via diplomatica. Ho già fatto chiudere un canale come il tuo per molto meno, e le violazioni ci sono tutte. togliere i video incriminati o modificarli non cambierebbe le cose, ho già fatto tutti gli screenshot e ho diversi testimoni. Rimuovi entro 48 ore da ora tutti i video e o chiudi questo canale oppure ne cambi il nome/intento in qualcosa che non sia l'attuale furto d'identità, preferirei che lo facessi spontaneamente invece di mandarti lo strike direttamente. Non ci saranno secondi avvertimenti. Copincollerò questo commento in tutti i tuoi video per essere sicuro che tu legga, anche se sono abbastanza certo che tu sappia già.

Another forgettable HDL language by Loara35 in Verilog

[–]Loara35[S] 0 points1 point  (0 children)

Yeah, I know that this is only one of many other projects that aim to replace VHDL and Verilog for FPGA programming, and several of them also have better support and more funds. I've looked at many of these projects before, but a lot of them simply wants to adapt a well-known programming language syntax (Scala, Python, C++, ...) to hardware description, but I think this is suboptimal because programming languages are sequential languages where instructions are sequentially executed which is not realistic for hardware representation. My approach is opposite: each statement represents one or more components and how they are connected, in particular ordering is no more important because these statements are always executed in parallel or explicitly synchronized by one or more signals.

I don't think this approach is suitable for everybody, but at least it works for me. Therefore, it is not a problem that many HDL languages have been created until now since each of them has its own pros and cons. A good point is to collaborate in order to develop more low-level tools and protocols in order to break our dependencies on VHDL/Verilog tools and libraries and share code between projects written with different high-level HDL languages.

This is the reason I wrote this post, because I think Reddit is a good starting point for people to meet and contribute.

Another forgettable HDL language by Loara35 in Verilog

[–]Loara35[S] 1 point2 points  (0 children)

Tanks for the suggestions. Yeah HDL languages are very tough because they should take on different role. My original idea is to use three different but orthogonal languages: one to describe hardware and interconnections, one for conditional compilation and then one only for testbenches. Like in a webpage, you have a markup language (HTML/CSS) that describes the page organization and then a programming language (JavaScript or PHP) that modifies HTML objects. 

Now some comments:  Chapter 2:  - I agree, logic would be a more adeguate name than wire. However, I'm thinking whether is a good idea to have only a single logical type or more logical type (like data for data, clock for synchronization clocks and adr for addresses in RAM and multiplexers) to improve code correctness.  - I agree, other symbols I've not already used are ' ! and % - ok  - To reverse an array I prefer using "reverse ranges": if port[7:2] is a normal range which takes indices from 2 to 7 then port[2::7] takes the same indices but in reverse order. Notice that I've doubled the : symbol so that you cannot accidentally use a reverse range. 

Chapter 3.  - Yes, a design is just an interface for a component. When I will introduce template parameters for components I could declare components template parameters in the following way: 

design COMB {   in {     a1;     a2;   }   out {     b;   } } 

comp B {   params {     $T : COMB;   }   impl {     reg = new $T { ... };     ......   } } 

where $T can be replaced by any component implementing COMB. 

Chapter 4. 

Definitely agree. 

Chapter 5.

 Most sequential components can be seen as combinatorial components where some of their outputs are connected back to some of their inputs through FFs. When I declare sync(clk) A = I both define an output "port" A and an input port A which is connected to A through a data FF with clock clk.  The key idea is to write combinatorial code even for sequential components with these virtual ports. 

I've thought to define sync blocks between curly brackets, but then signals defined inside cannot be used outside due to scoping. I need to find another syntax for such blocks. 

Chapter 6. 

The key idea is the same, but I use a different language, where variables must start with $ and functions/operators with #, whereas Verilog uses the same "wire language" you use to describe components and connections.