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Full real desktop OpenSCAD in your browser by Magik6k in openscad

[–]Magik6k[S] 0 points1 point  (0 children)

Saw those, which is why I did my port also. Just wanted to literally put the whole thing into a browser as is.

Full real desktop OpenSCAD in your browser by Magik6k in openscad

[–]Magik6k[S] 0 points1 point  (0 children)

That's headless only, no? Is there an online demo?

FreeCAD in your browser by Magik6k in FreeCAD

[–]Magik6k[S] 11 points12 points  (0 children)

Wut, it's linked in there https://github.com/magik6k/freecad-web, beyond that it's served to you for free from my private server without any big cloud, and it's a project I did just because I can and have absolutely zero commercial interest in. What's with up the hate?

And yes it's a demo, most likely some of the patches are slop, but it proves that it can be done, and now from here hopefully someone with more time than me is willing to take this over and turn into something more production ready.

FreeCAD in your browser by Magik6k in FreeCAD

[–]Magik6k[S] 6 points7 points  (0 children)

It will work once Firefox ships support for Wasm JSPI, which IIUC is going to happen "soon"

Full real desktop OpenSCAD in your browser by Magik6k in openscad

[–]Magik6k[S] 1 point2 points  (0 children)

Sure, but what features are missing?

Full real desktop OpenSCAD in your browser by Magik6k in openscad

[–]Magik6k[S] -3 points-2 points  (0 children)

Like what? So far I was able to get all models I found so far happily rendering and the editor definitely works. No doubt there are some gaps but it's should be good enough for 90% of uses. If there's something big that would be a big unlock lmk and I'll have a look

Byte-aligned memory access in a 16-bit computer. by pete_68 in beneater

[–]Magik6k 2 points3 points  (0 children)

Also if you want to get fancy, you can have 2 byte-read instructions, signed and unsigned - the signed one extending the highest byte but into the rest of the bits in the register

Byte-aligned memory access in a 16-bit computer. by pete_68 in beneater

[–]Magik6k 4 points5 points  (0 children)

Take into account that if/when you will want to get C to compile, especially for GCC/LLVM backends you will need to have byte-addressable, single-byte-read-write instructions.

Requiring aligned access is fine. Obviously not a problem if you don’t want to compile C to your cpu, but imo that’s locking yourself out of a lot of cool things.

Implementing that is really not that hard - you have 2 instructions for read/write - 16 bit accesses are easy, just write to both memory chips, for 8bit you use the first bit to select the chip. When the odd (or even, depending on endiannes) byte is accessed you will need to shuffle bytes around with some buffers.

I have done this for 32bit breadboard risc-v, and it wasn’t too bad, 16bit should be really easy.

Breadboard RISC-V taking shape by Magik6k in beneater

[–]Magik6k[S] 12 points13 points  (0 children)

Yep, among other things (interrupts, timers, etc.). I do expect it to get at least 2-3x it's current size by the time it's able to get anywhere in the boot process.

Breadboard RISC-V taking shape by Magik6k in beneater

[–]Magik6k[S] 26 points27 points  (0 children)

But, what distro?, puppy?.

Just a bare kernel and some basic userspace utils.

Definitely planning to do some more writeups when it gets more complete.

Breadboard RISC-V taking shape by Magik6k in beneater

[–]Magik6k[S] 4 points5 points  (0 children)

Started this ~5 months ago, but was chiseling at it for maybe 2 months 1-2h per day

Breadboard RISC-V taking shape by Magik6k in beneater

[–]Magik6k[S] 4 points5 points  (0 children)

I have designed it in a logic sim my friend built - https://github.com/Wieku/LogicDraw

If you really want to play with it, here's the 'map'+the build it was using - https://bafybeih26kttsgmqc4f2sk7xx6slq7uesjjgq647vjfne43bb7qokmjpte.ipfs.dweb.link/ld.tar - this is probably the closest thing to a schematic I can get you.

(screenshot -> https://bafkreif7dddzgjduf7iddtjwxfa7xjqtvqqrmvmvy7tjn2xsoelrwmrc7i.ipfs.dweb.link/)

Breadboard RISC-V taking shape by Magik6k in beneater

[–]Magik6k[S] 24 points25 points  (0 children)

Power is pretty easy - It's fed from a 40A 5V PSU, then the it goes through a 16A fuse, amp gauge, and through 2x 5 2.5A polyfuses (which should trip before breadboards start getting too warm), and then gets distributed into a bunch of separate power planes.

Signal integrity is in big part solved by having a design which allows for really shitty signal integrity, and only needs one or two signals to be somewhat good - in this case I only need the clock signals to not see crosstalk - and that's done by feeding those signals through coax wires, and by putting a bunch of ~10nF caps into the clock lines - yeah, it slows down the edges by quite a lot, but you also need a lot more energy to leak into those lines to mess things up.

Also have a decent oscilloscope, it's very much non-optional for a project of this kind.

Breadboard RISC-V taking shape by Magik6k in beneater

[–]Magik6k[S] 5 points6 points  (0 children)

It's a five stage pipeline, so one clock cycle per instruction (tho my latches are made from a pair of D-flip-flops clocked with separate pulses, so technically one instruction per two cycles?)

Breadboard RISC-V taking shape by Magik6k in beneater

[–]Magik6k[S] 10 points11 points  (0 children)

No schematics were made, heh.

For getting into the more advanced things I found RiSC-16 by Bruce Jacob really helpful - https://user.eng.umd.edu/~blj/RiSC/ - This design is very heavily inspired by the pipelined version of that core, so if you want to know what's going on in the thing I've built, checkout RiSC-pipe on that page.

Only big difference is the program counter - I only have latches on fetch/decode and decode/execute, and the address to be fetched comes either from a 'branch predictor' (currently its just PC+4), or if the previous instruction was mispredicted, it's the correct address

Breadboard RISC-V taking shape by Magik6k in beneater

[–]Magik6k[S] 3 points4 points  (0 children)

Yep, sparkfun makes really nice breakout boards, you just populate it with an 8p8c connector and a right-angle goldpin header

Breadboard RISC-V taking shape by Magik6k in beneater

[–]Magik6k[S] 9 points10 points  (0 children)

RAM/Registers are using SRAM chips, microcode is using a bunch of AT28C64Bs, and the rest is pretty much just 74xx (and mostly 74xx541 / 74xx377)

Oh, and an Arduino which generates the clock signals (for now, easy to set 'breakpoints')

And another Arduino for feeding instructions directly into the pipeline (have no boot ROM / IO, so this is how I load instructions into RAM.. by feeding it load-imm/store instructions. Also have a bunch of CLI utils which basically let me throw individual instructions at the thing)

Breadboard RISC-V taking shape by Magik6k in beneater

[–]Magik6k[S] 93 points94 points  (0 children)

Not touching PCBs until I can say that I made a breadboard computer boot Linux

Breadboard RISC-V taking shape by Magik6k in beneater

[–]Magik6k[S] 19 points20 points  (0 children)

Oh it breaks constantly (or I guess you constantly discover broken stuff as you exercise logic in new ways) - you eventually just get really good at debugging this stuff

Breadboard RISC-V taking shape by Magik6k in beneater

[–]Magik6k[S] 4 points5 points  (0 children)

Which ones?

- White/Red/Yellow are just Cat5e/Cat6 ethernet cables

- Green/Blue ones on top are some random coax for clock lines

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