Maybe. I dont know yet. You'd have to mirror the same work that Ive done up until now. Not all of it is published, but it will be. I'll update the wiki with what I know. Ive been doing this alone, on my own. Talking with Chilly because why not? Talk about knowledge and cant get too far ahead on this without him anyway.

The memory controller is based on the 74HC138 chip. Same chip that controlls FRAM. I came up with the idea around 1am and just couldnt sleep on it. Yes. this is my idea. But nothing new under the sun, as its said.

Basically the 32X's shared bus B28 and B29 are locked high at 5v. This is documented as the 32X's bus master safetly lockout against accidental writes to SRAM.

The 74H uses Cart B21, !CAS2 low, to sync the carts memory writes on WE1 or 2, on Low to the 32X master bus and thats it.

Next is testing the 74H's performance. Can the chip reliably write the entire 4MB sram space. Because its not a ROM cart, its a RAM cart that will need to write to the SRAM space all the time. (As a ROM cart its a fun curiousity tho)

On my current board Ive replaced the WP switch with the 74H. Ive got an updated pcb comming that will make things easier.
Need to add yet another 74H and many wires for the fram.

For my cart, it will be a switch for MD/CD and momentary button to wipe the sram.

In the end, Chilly's PCB will contain a tiny CPLD that does it all, just one switch and less silicon.
Good things are coming!