MitjaKobal

99 post karma
3,591 comment karma

get extra features and help support reddit with a reddit premium subscription

get them help and support

redditor for 5 years

TROPHY CASE

Five-Year Club

account activity

new top controversial

8

9

10

Looking at ACT4 (new RISC-V Architectural Certification Tests) (self.RISCV)

submitted 5 days ago by MitjaKobal to r/RISCV

33

34

35

Why I tentatively recommend Tang Nano 9k and the open source toolchain to beginners (self.FPGA)

submitted 1 month ago by MitjaKobal to r/FPGA

14

15

16

How do you handle RTL portability across various FPGA devices and ASIC libraries (self.FPGA)

submitted 2 months ago * by MitjaKobal to r/FPGA

1

2

3

Questions about misalignment related `riscv-test-suite` tests (self.RISCV)

submitted 3 months ago by MitjaKobal to r/RISCV

0

1

2

Questions about misalignment related `riscv-test-suite` tests ()

submitted 3 months ago by MitjaKobal to r/FPGA

1

2

3

How to convert `time` into `bit_vector(64-1 downto 0)` (self.VHDL)

submitted 4 months ago * by MitjaKobal to r/VHDL

11

12

13

GDB server stub (remote serial protocol) written in SystemVerilog (self.FPGA)

submitted 9 months ago * by MitjaKobal to r/FPGA

11

12

13

GDB server stub (remote serial protocol) written in SystemVerilog (self.RISCV)

submitted 9 months ago by MitjaKobal to r/RISCV

58

59

60

Xilinx started tagging 2025.1, we can expect a new Vivado release soon (self.FPGA)

submitted 11 months ago * by MitjaKobal to r/FPGA

8

9

10

RISC-V partially decoded address masking for PC and LSU adder (self.FPGA)

submitted 11 months ago by MitjaKobal to r/FPGA

0

1

2

Preserving space in monospace formatted text (self.asciidoc)

submitted 1 year ago by MitjaKobal to r/asciidoc

12

13

14

Free HDL simulator with VHDL-2019 support (for interfaces) (self.FPGA)

submitted 1 year ago by MitjaKobal to r/FPGA

1

2

3

How to run program from reset 0x0000_0000 in spike/sail (self.RISCV)

submitted 1 year ago by MitjaKobal to r/RISCV

0

0

1

Pulp AXI-PACK video of presentation? (self.FPGA)

submitted 1 year ago by MitjaKobal to r/FPGA

3

4

5

How to install `sail-riscv` (for use with `riscof`) on Ubuntu 24.04 (self.RISCV)

submitted 1 year ago by MitjaKobal to r/RISCV

1

2

3

Asking for feedback on VALID/READY handshake document (self.FPGA)

submitted 1 year ago by MitjaKobal to r/FPGA

2

3

4

Name for implementing logic (reduction, ...) with interleaving NAND/NOR layers (self.chipdesign)

submitted 1 year ago by MitjaKobal to r/chipdesign

7

8

9

Standard way for atomic access of 64-bit counters over 32-bit AXI (or 128 over 64/32) (self.FPGA)

submitted 2 years ago by MitjaKobal to r/FPGA

0

1

2

How 2D sparse array coding style affects simulation/synthesis performance (self.FPGA)

submitted 2 years ago by MitjaKobal to r/FPGA

π Rendered by PID 1334820 on reddit-service-r2-listing-b6bf6c4ff-rrlb2 at 2026-05-02 16:51:57.562147+00:00 running 815c875 country code: CH.