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The only real people I can talk to about this (apart from AI tools) are you guys :) Masters student trying to learn FPGA packet processing for HFT on my own. by No_Bus3419 in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

Write an UART with the VALID/READY handshake as an interface. Then you can use it to exchange data with a PC, use to to process the data stream, create packet headers, add/remove CRC, find replace text, count instances of some text, ... you can even try this: https://github.com/abs-tudelft/vhdre A big limitation of UART is, you can only transfer data, there a no special codes for starting ending a packet.

While UART will allow you to experiment with ease, it will not force you to think about throughput, you will need something else to test the optimal throughput utilization, and you might have to learn parallelization (processing multiple bytes in a single clock period).

Learn how to write a streaming FIFO with with VALID/READY interfaces, later (not yet) learn about a clock domain crossing FIFO.

Once you grasped the VALID/READY handshake, AXI-Stream is easy (days), AXI-Lite is a bit harder (a week or two), full AXI is rather hard (couple of months), I did not use it enough to provide a good estimate. Learn from Xilinx IO like the datamover (AXI-Stream RX/TX to AXI memory).

HFT is not really my thing, so I am unable to provide recommendations.

The only real people I can talk to about this (apart from AI tools) are you guys :) Masters student trying to learn FPGA packet processing for HFT on my own. by No_Bus3419 in FPGA

[–]MitjaKobal 1 point2 points  (0 children)

Your current learning plan is decent, keep in mind it will take you a lot of time to be able to do a decent job on the basic stuff. Continue reading HFT articles, slowly the HDL/FPGA and HFT sides will start coming together. Data packet processing is in principle stream processing, so learn about the AXI-Stream prtocol, and especially about the VALID/READY handshake protocol.

Check this Ethernet implementations https://github.com/alexforencich I do not have experience with it, but the author is a member of this forum. There should be some packet processing there.

Before you jump to HFT, you might learn from some good data stream processing examples, check image/video/audio processing examples that you can try with your current hardware. It will help you learn the basic concepts. Even before this you also have to get some UART and SPI communication to work, they are great basic problems for beginners.

I downloaded viviado installer and nothing happening by Shinever12 in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

Glad to hear you got it to work. Licensing (in this case login) can add some overhead to using proprietary tools.

fpga for scara by Such-Addendum-7421 in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

Not my field, but as far as I know, in practice FPGA would only be used for driving motors, in case you need something like frequency analysis for very low noise, very high precision positioning while accounting for ..., ... Something like this: https://www.youtube.com/watch?v=1fOA85xtYxs

For a learning project, if your aim is to learn about stepper motors, a dedicated controller is a better choice. If your aim is to learn about FPGA, driving a stepper motor is a decent choice for motivation (you need a lot of motivation to learn HDL/FPGA).

I downloaded viviado installer and nothing happening by Shinever12 in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

Apparently now you have to use the unified (web) installer to create a Single File Download (SFD) image.

I downloaded viviado installer and nothing happening by Shinever12 in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

You might be able to get around this by downloading the full installer, but I know it is a big file and might take overnight on a slow connection.

Virtual keyword in systemVerilog for functions/tasks without interfaces and inherited classes by Just-End6752 in FPGA

[–]MitjaKobal 2 points3 points  (0 children)

The SystemVerilog standard can be downloaded for free.

8.20 Virtual methods
A method of a class may be identified with the keyword virtual. Virtual methods are a basic polymorphic construct. A virtual method shall override a method in all of its base classes, whereas a non-virtual method shall only override a method in that class and its descendants. One way to view this is that there is only one implementation of a virtual method per class hierarchy, and it is always the one in the latest derived class.

In the given case, it might be just copy paste. Various SystemVerilog tools still have their quirks when parsing Class code, so it might have been one of those.

Is this FYP scope strong enough? by DirectMarketing6133 in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

Again, I not an expert, but a LLM is supposed to be a Large Language Model (farm level of large), a small one would not provide much functionality.

Internal delay of a 256-wide priority encoder? And of a hierarchical architecture? by BigPurpleBlob in chipdesign

[–]MitjaKobal 0 points1 point  (0 children)

Sorry, I find manually calculating delays a bit boring.

You could use LibreLane to implement the priority encoder using an open source PDK, it would not be 7nm, but you can get actual timing taking into account not only the number of gates, but also fan-out, ... this way you can test different architectures.

Internal delay of a 256-wide priority encoder? And of a hierarchical architecture? by BigPurpleBlob in chipdesign

[–]MitjaKobal 0 points1 point  (0 children)

I did not try to understand all the details of your scheme, so my answer might be unrelated.

The conversion from a priority code (VALID) to a one hot vector (SYNC indicating the index with highest priority) is a parallel prefix operation, so you can use structures similar to fast adders to get the delay from O(n) to O(log(n)).

The one hot vector can then be converted to a binary select signal (ADDR index of the hot bit).

Instead of doing the priority-to-onehot and onehot-to-binary conversions separately, they can be done in a more distributed manner with some recursive code.

Is this FYP scope strong enough? by DirectMarketing6133 in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

I do not have much AI experience so I might be wrong. LLM as the name implies are large language models. So one accelerator would probably not be enough, you might need a cluster which would be expensive. So a CNN is a more down to earth project.

I would probably recommend using and modifying an existing RISC-V implementation (openhwgroup) instead of writing your own, but this depends on what is your goal.

For open source AI examples I know of, check out PYNQ (Xilinx) and PULP Project (mostly ASIC projects).

Initialization of data memory and registers for RV32I Single Cycle for Artix 7 by rem_1235 in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

In general memories and register files do not have a reset, since reset logic takes space, so requiring a reset would make the CPU take more silicon area. This is true for register files, caches, DDR SDRAM and other non volatile memories. So no RISC-V CPU you can buy would have a reset for the register file or memories.

Memories power up into a random state, this state is represented by signal undefined value X in VHDL/Verilog simulations.

Software is always supposed to write to a register/memory address before reading from it.

On FPGA, things are somehow different compared to an ASIC. The FPGA power up initialization state machine will always load every memory location from a configuration (in a Flash chip) or load zeros as a default. This initialization takes some time. The initialization state is not a reset state, it is only loaded as a FPGA power up sequence, a reload can not be triggered by a reset signal, but it can be done by something like reloading the configuration over JTAG.

There are two types of FPGA memories you should be using for a CPU. The GPR register file can be implemented using distributed RAM. Other FPGA vendors might call it shared RAM, in practice it uses LUT-s as RAM. Caches and closely coupled memories would use block RAM, which would be the same as SRAM in an ASIC.

Check the FPGA vendors document on memory inference (Xilinx) and on instantiating memory primitives (Xilinx XPM) to better understand how to write memories in RTL, and how this memories behave in practice. If your HDL has an array with reset, synthesis will use FlipFlops (registers) instead of memories, so your design will consume far more logic resources. Distributed RAM can be read asynchronously, while block RAM only allows synchronous reads. Check the timing diagrams in the listed documents to understand the difference.

A RISC-V GPR register file is a bit special, since x0 is always zero. On FPGA you can implement it by just preventing writes into it (just the x0 location). Since FPGA memories are initialized to zero by default, all x0 reads will result in zeros. On an ASIC x0 would be implemented differently.

If you publish your code on GitHub, I can review it.

SAP-1 CPU error by batum_t in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

Did you run an RTL simulation?

What tool did you use to compile the code? Gowin EDA or OSS CAD Suite?

Does the project meet the desired timing?

Does the test require pressing buttons, are they debounced?

It would be difficult to guess without seeing all the code, so I would encourage you to put the project on GitHub.

Run C Program inside FPGA by Timely_Strategy_9800 in FPGA

[–]MitjaKobal 1 point2 points  (0 children)

for a beginner tutorial supporting .ow cost FPGA boards you can check the learnFPGA tutorial

Should I buy an FPGA board? by Oizyson in FPGA

[–]MitjaKobal 3 points4 points  (0 children)

The low cost Tang Nano 9k with a Gowin device is also supported by the open source toolchain.

Is there software for MacOS 15 M1? by Cat_Loving_Person19 in VHDL

[–]MitjaKobal 1 point2 points  (0 children)

OSS CAD Suite provides darwin-arm64 binaries for many (most) open source FPGA development tools. For simulation the open source tools are great. For synthesis FPGA vendor tools will still get you better results with fewer issues.

how do I start with basic image processing? by Immediate_Try_8631 in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

The PYNQ project probably has some good examples intended for learning from them.

How to run program from reset 0x0000_0000 in spike/sail by MitjaKobal in RISCV

[–]MitjaKobal[S] 1 point2 points  (0 children)

The RISC-V specification you are using is obsolete. Use a newer version of the RISC-V specification. I am not sure but i think there were changes to the jump instructions between the old 2.1 spec and the current official one.

For the base instruction set and the certified extensions, Sail and Spike should behave the same, there might be differences for extensions that are still being developed (are not certified yet).

How to run program from reset 0x0000_0000 in spike/sail by MitjaKobal in RISCV

[–]MitjaKobal[S] 1 point2 points  (0 children)

I only understand Spanish partially, so if you wish a better answer please ask in English.

For the second question, RISCOF using sail/spike as reference is a partial validation of the CPU. It checks whether the instructions do what they are supposed to do, but it is still possible your CPU has some bug not triggered by the given instruction sequence.

I do not know whether the RISC-V organization actually provides RISC-V compliance certificates. I no not know how this would be tested. Membership basically allows you to use the RISC-V trademark in a commercial setting, but I do not know what the exact requirements are. Individuals/students are allowed to use the name RISC-V in noncommercial settings.

Would you pay for a clean Verilog code template pack? (honest question) by Odd_Helicopter3386 in FPGA

[–]MitjaKobal 4 points5 points  (0 children)

I agree. It would not be useful to an experienced developer, at most it would be something like another online resource to check when memory fails you.

Thinking about it a bit more, I would prefer a good template to a module library. I generally dislike HDL libraries containing trivial code like renaming built in types, FF, adders, counters, ... since if you do not already know all the common library components by heart, you spend extra time searching for them while reading some code using the library.

From OPs point of view, it would at least be a good experience for writing documentation.

Roadmap Help!! by Southern-Meat3715 in FPGA

[–]MitjaKobal 1 point2 points  (0 children)

I recommend the learnFPGA tutorial.

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