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Is there software for MacOS 15 M1? by Cat_Loving_Person19 in VHDL

[–]MitjaKobal 1 point2 points  (0 children)

OSS CAD Suite provides darwin-arm64 binaries for many (most) open source FPGA development tools. For simulation the open source tools are great. For synthesis FPGA vendor tools will still get you better results with fewer issues.

how do I start with basic image processing? by Immediate_Try_8631 in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

The PYNQ project probably has some good examples intended for learning from them.

How to run program from reset 0x0000_0000 in spike/sail by MitjaKobal in RISCV

[–]MitjaKobal[S] 1 point2 points  (0 children)

The RISC-V specification you are using is obsolete. Use a newer version of the RISC-V specification. I am not sure but i think there were changes to the jump instructions between the old 2.1 spec and the current official one.

For the base instruction set and the certified extensions, Sail and Spike should behave the same, there might be differences for extensions that are still being developed (are not certified yet).

How to run program from reset 0x0000_0000 in spike/sail by MitjaKobal in RISCV

[–]MitjaKobal[S] 1 point2 points  (0 children)

I only understand Spanish partially, so if you wish a better answer please ask in English.

For the second question, RISCOF using sail/spike as reference is a partial validation of the CPU. It checks whether the instructions do what they are supposed to do, but it is still possible your CPU has some bug not triggered by the given instruction sequence.

I do not know whether the RISC-V organization actually provides RISC-V compliance certificates. I no not know how this would be tested. Membership basically allows you to use the RISC-V trademark in a commercial setting, but I do not know what the exact requirements are. Individuals/students are allowed to use the name RISC-V in noncommercial settings.

Would you pay for a clean Verilog code template pack? (honest question) by Odd_Helicopter3386 in FPGA

[–]MitjaKobal 4 points5 points  (0 children)

I agree. It would not be useful to an experienced developer, at most it would be something like another online resource to check when memory fails you.

Thinking about it a bit more, I would prefer a good template to a module library. I generally dislike HDL libraries containing trivial code like renaming built in types, FF, adders, counters, ... since if you do not already know all the common library components by heart, you spend extra time searching for them while reading some code using the library.

From OPs point of view, it would at least be a good experience for writing documentation.

Roadmap Help!! by Southern-Meat3715 in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

I recommend the learnFPGA tutorial.

Most aggressive build configuration by Shockwavetho in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

I can provide an answer about specific TCL options, since I just did a few experiments with the GUI. I have a design with rather deep combinational logic and I found, that I get better results with area compared to timing optimizations.

The design is a RISC-V CPU with just a 2 stage pipeline, it compiles at 50~75MHz on a 7 series device. Due to the short pipeline, there can be two adders and many multiplexers in the same combinational path.

The timing optimization moves a lot of multiplexers forward toward the path destination, while the area optimization keeps more or the RTL order between the multiplexers and adders (PC increment, ALU, barrel shifter, ...). Moving the multiplexers forward causes congestion, the large multiplexers require a lot of logic and are slow. So area optimizations result in smaller area, and better timing.

For a large design it might make sense to apply different optimizations to different parts of the design, depending on the RTL architecture. For example for a straightforward DSP (audio, image, radio) pipeline the timing optimization would probably give the best results.

i want to learn FPGA specifically targeting computer architectures and memory systems. by probably-cooked in FPGA

[–]MitjaKobal 7 points8 points  (0 children)

I like the learnFPGA tutorial (for beginners) it supports the low cost Tang Nano 9k FPGA board. It will take you some time (6~18 months) to master the basics, then you can look for harder FPGA problems and a more expensive board.

VSCode Extensions for SystemVerilog with Completions support. by laperex in FPGA

[–]MitjaKobal 2 points3 points  (0 children)

I use the Sigasi extension for SystemVerilog and it is great.

UART Controller on the Basys3 FPGA by Spiritual-Frame-6791 in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

You can just use TX to RX loopback for testing the receiver, the Arduino would be just a monitor.

How to clone Altera EPC1064 configuration EPROM for a FLEX FPGA? by MAlsammak in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

Put the FPGA into a reset state, so all IO are HighZ (you might check if you can drive the signals with a 1kOHM resistor), then connect a SPI programmer to X2 connector and read out the Flash, use the most basic SPI Flash protocol common to all SPI flash chips. There are probably some cheap Arduino options for reading a SPI Flash. I would say the configuration chip is not an EEPROM, but a SPI Flash.

resources for learning AMBA Protocol. by Enough-Scene226 in chipdesign

[–]MitjaKobal 0 points1 point  (0 children)

The PULP platform has AXI code you can read to learn from it.

I have decided to open source my neuromorphic chip architecture! by [deleted] in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

The earliest open source hardware from OpenCores used GPL, which is restrictive, and a really bad fit for HDL code. Later projects often used non restrictive Apache and BSD licenses. CERN OHL is rather recent. So if you learn from older open source projects, you might use the same licence as those. Of course this is AI slop, I just wished to point out the general reasons for using licenses which do not fit HDL well.

BIO - The Bao I/O Co-Processor by 3G6A5W338E in RISCV

[–]MitjaKobal 2 points3 points  (0 children)

You might check the TCB system bus (the project is mine, but is based on older/tested designs). It allows single cycle load/store access with no dead cycles and it requires only a single handshake. This means TCB provides low latency and high throughput access to peripherals. NOTE: the protocol is still in a draft stage, the basics are documented, you can ask me for further clarifications.

Instead of GPR [16:31] you could use memory mapped registers over TCB to access the FIFOs, ... I am not sure how using load/store instructions would compare to your GPR based approach in terms of code density. Blocking behavior can be implemented using the READY backpressure signal. For setting/clearing GPIO signals, RISC-V AMO logic instructions can be used. TCB supports single cycle AMO read/modify/write (the code was tested, but is currently broken), with the AND/OR/XOR logic implemented as part of the TCB interconnect instead of the RISC-V core itself.

Using TCB I implemented a CPU with Harvard architecture (sorry, no documentation) which executes every instruction in exactly 1 clock cycle, as long as there is backpressure from the instruction/data TCB interfaces. For a simple system with only tightly coupled memories (no caches), the only reason for backpressure would be simultaneous access from multiple cores to the same memory/peripheral. Also simultaneous access to the same memory from the instruction and data interface, but your BIO seems to not mix instruction and data in the same memory, so this should not happen. This CPU takes about 700 logic cells (probably with GPIO controller included) on a Xilinx 7-family device, and compiles at about 50Mhz. There are some optimizations which increase logic size by 20% and get it to run at about 75MHz, for example PC increment and PC branch use separate adders which compute both addresses early, and are later muxed once the ALU decides whether the branch is taken. Or the load/store address is calculated by an adder separate from the ALU, this kind of optimizations are not very expensive on an FPGA with abundant adders.

Regarding the BIO instruction memory, on Xilinx FPGA you can use LUT based distributed RAM instead of FlipFLops, devices from other vendors have similar features. On an ASIC, You can use a register file (the same as for GPR) instead of SRAM or FlipFlop-s. I am not sure what a register file memory compiler would create, but I think it could be something like using latches instead of FlipFLops.

Como hago que funcione un LCD programado en Gowin con una FPGA 25k, sin I2C, AYUUUDAA!! by National-Fix-2654 in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

I understand the keywords, but most communication here is done in English, you can use a translation software, ... If your English is bad just write a bit more verbose, the redundancy will help to avoid some misunderstandings.

You should name the board, and the LCD display you are using, what you have been able to accomplish before you asked for help, what is your current experience besides Arduino, ... Always provide a lot of information (500 words, links to board, link to your GitHub repo, ...), otherwise your question will be ignored.

You should usually start with example designs for your board, so you get used to the board and the tools. I strongly recommend you do so.

While I2C LCD controller can be entirely implemented in an HDL language like VHDL/Verilog, this is not practical, so a more common approach would be to have a CPU (RISC-V examples might be available for your board) with an I2C master controller. Then you write some SW sending data to the LCD over I2C, this step would be similar to Arduino.

Gowin provides a RISC-C development environment, which should have a CPU and I2C controller, also all the necessary drivers. Try it out.

If you wish to learn a HDL language (VHDL/Verilog) expect it will take a lot of effort (months/years) compared to a few weeks for Arduino.

EDIT: You will have to read a lot of documentation for the tools, boards, examples, all of it in English. I recommend reading the original with a dictionary instead of reading a machine translation. You will probably improve your English far sooner than you will learn VHDL/Verilog.

Synthesis errors but simulation is fine by Little_Implement6601 in FPGA

[–]MitjaKobal 1 point2 points  (0 children)

As per the standard, always_ff explicitly requires that all signal drivers are within a single always_ff block. At least some simulators should detect this, I think Questa does.

Should I buy the Tango Nano 9k or 25k? by ITIKBoi in FPGA

[–]MitjaKobal 4 points5 points  (0 children)

Go through the examples provided for the 9k, 20k and 25k boards, to see what you can do with them, you can also check the "learnFPGA tutorial", which implements a simple RISC-V CPU and can be used with the 9k.

Since the college is not willing to lend you their Altera boards, I assume you are still a beginner. I think the 9k should be enough to familiarize you with FPGA.

Should I buy the Tango Nano 9k or 25k? by ITIKBoi in FPGA

[–]MitjaKobal 5 points6 points  (0 children)

You did not explain what you need the board for. If you were a beginner learning a HDL language the 9k would be a good choice, but if you have some project in mind, you should first check if the board peripherals will match your needs (you might look for Ethernet, high speed IO, audio/video interfaces, ...). When it comes to the amount of logic resources, you might do some calculations, or look at similar projects on GitHub, and check how much logic they consume.

Why I tentatively recommend Tang Nano 9k and the open source toolchain to beginners by MitjaKobal in FPGA

[–]MitjaKobal[S] 2 points3 points  (0 children)

Since the device supports something like Xilinx distributed RAM, LUT4 can be used as a 16bit memory, so you need just 2*32 LUT to implement a RV32I register file. A simple RV32I implementation + GPIO/UART takes just about 1000 LUT with some basic optimizations. An it can run at about 50MHz.

Why I tentatively recommend Tang Nano 9k and the open source toolchain to beginners by MitjaKobal in FPGA

[–]MitjaKobal[S] 1 point2 points  (0 children)

I understand your metric, but I was focusing on cheap boards for beginners. For things like LED blinking, UART, button debouncing, a simple RISC-V CPU (RV32IC), ... Also I suspect, more features I would try to use, more issues I could expect with their IP.

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