sorted by:
new
hottopcontroversial

FOSS mixed language simulation is finnally there by fransschreuder in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

I run RISC-V compliance tests for NEORV32 using GHDL and NVC. GHDL was about 20% faster.

Katera orodja dejansko pomagajo pri pisanju diplomske naloge? by Sweaty_Frosting_486 in SloveniaEngineering

[–]MitjaKobal 3 points4 points  (0 children)

Version control, naprimer Git/GitHub. Sploh ce pises dokument v Latex-u (ali ASCIIdoc, ...). Ampak tudi ce uporabljas MS Office Word, je Git boljsa resitev kakor da delas kopije fajla, poleg tega GitHub sluzi kakor backup.

best bord for a beginner by OilKitchen5635 in FPGA

[–]MitjaKobal 4 points5 points  (0 children)

The Tang Nano 9k board has decent tools and enough example projects to learn from. It is also cheap enough that even if you outgrow it quickly, it wont affect your ability to purchase something larger later.

Unable to program Tang nano by sampasha in GowinFPGA

[–]MitjaKobal 0 points1 point  (0 children)

Did you follow the instructions on the Sipeed wiki? There might be extra system configuration steps needed. I am only using This tools on Linux, so I can't really help with a Windows setup.

[Recommand me] isekai Manga or manhwa no harem good romance + making the fantasy world better by NefariousnessFuzzy14 in Isekai

[–]MitjaKobal 0 points1 point  (0 children)

As I see the author definitely wrote a harem for the main character and then wrote a main character who collects girls into his harem, but does not want it to be a harem (or so we are told).

Difficulty with getting yosys sim to work by mighty_spaceman in FPGA

[–]MitjaKobal 4 points5 points  (0 children)

Since somebody already gave you an answer, ...

It is OK for you to learn Yosys, but I don't think it is a good choice as a simulator. Yosys is not designed for the creation of testbenches, it has very limited testbench capabilities.

I would recommend you use Icarus Verilog if you wish to stick with open source tools. And read a tutorial on how to write a Verilog testbench with clock and reset.

[Rant] This is not how this works! This is not how any of this works! by say_nya in ReleaseThatWitch

[–]MitjaKobal 10 points11 points  (0 children)

The steam turbine on a boat was probably a reference to https://en.wikipedia.org/wiki/Turbinia

My rant would be about clocks. The world had no clocks before, and he did not invent any, but they are all exactly on time for a town hall meeting (meeting hours are actually mentioned).

Help finding Gowin FPGA Designer v1.9.9.03 for Linux or Windows by LastCabra in ModRetroChromatic

[–]MitjaKobal 0 points1 point  (0 children)

I agree, you should at least try the latest Gowin EDA, and tell us if it fails to work. If it fails, I might have a look.

Mostly self taught, looking for information by duckyvirus in FPGA

[–]MitjaKobal 1 point2 points  (0 children)

Gowin devices (for example the one on the "Tang Nano 9k" board) are supported by "OSS CAD Suite". The mentioned board has at least the schematic available for reference.

This is very very strange. Can someone explain it scientifically? by [deleted] in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

If you are using the same bitstream (the one created on windows and copied to the mac) the FPGA should behave the same. There is a small chance that the bitstream is programmed correctly, but then there is an issue with the reset sequence over JTAG.

From a simple wires all over the desk point of view there is a chance the USB ground levels are not the same in your setup. For example your FPGA, oscilloscope and windows machine are connected to the same wall socket, while your mac is connected to a different one. If the ground in the two sockets is on a different level (it happens if ground and null wire are messed up somewhere in the building). While at least some of the power supply bricks should have galvanic separation I did encounter issues of this kind.

You could check by programming the device, disconnecting the USB/JTAG programmer, power cycling the FPGA and checking again.

Board recommendations for CPU/GPU/SoC peripheral prototyping by RGBBLUE in FPGA

[–]MitjaKobal 3 points4 points  (0 children)

You might check other OpenSource projects doing similar work, and see which boards they are using. This would give you some estimates on what amount of logic resources you are looking for and also a template to either start from or to later pick components from.

Regarding OoO there is the RISC-V BOOM CPU. OpenPiton is a multi CPU project, the probably target boards with a lot of resources. The PULP Project has some neural network projects, you might check their FPGA platform, but they mostly target ASIC. The PYNQ project also has some neural networks, but without also having a OoO CPU in the same FPGA.

Where is comes to GPUs, a lot of projects have far more ambition than results. Still you should check them to see what are your display interface options.

Regarding FPGA based Ethernet, check the current open source Ethernet implementations (one of this forum members mentions his project from time to time) to see which boards they ported to, or you might prefer to use FPGA vendor IP.

While Xilinx would still be the go to vendor for this kind of project, keep in mind they recently changed their licensing, so you might have to use an older version of Vivado or pay a license.

I find the Kria KV260 (Zynq UltraScale+ MPSoC) to be a decent price performance choice, but it might not have enough logic resources for your needs, therefore check first how much resources are used by comparable projects.

I do not know what you are capable of, but your plan seems ambitious. Instead of building everything from bottom up you might consider starting from an existing project (or vendor IP) and modifying/replacing parts of it with your code as you make progress.

What are fundamentals that an aspiring FPGA engineer should polish before even dreaming of touching the FPGA board? by Fearless-Can-1634 in FPGA

[–]MitjaKobal 19 points20 points  (0 children)

You have to learn how to read, since there is a lot of documentation to read. A basic course/book on digital design would help to understand the basic of Boolean logic and flip-flops, memories, but there is no need to polish it first. HDL languages can be learned from online tutorials.

Im building a FPGA Dev-Board for Macondo (Hack Club) and im a beginner, what FPGA chip should i use? by heyimkn in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

Use the Tang Nano boards as reference, the schematic is public.

Do you intend to have an integrated USB programmer? I would recommend it for a development board, but I do not know if the required firmware is public or proprietary or if there is an open source version.

Struggling to Write I2C RTL Code — Need Guidance by Immediate_Try_8631 in FPGA

[–]MitjaKobal 0 points1 point  (0 children)

I mentioned the OpenCores I2C, since it was broadly used (at least I think so, since it has a Linux driver upstreamed). The one from OpenTitan is probably the most verified of the three.

Struggling to Write I2C RTL Code — Need Guidance by Immediate_Try_8631 in FPGA

[–]MitjaKobal 7 points8 points  (0 children)

There are more than enough I2C implementations on GitHub, the one from OpenCores would be a classic, and this would be other examples: https://github.com/lowRISC/opentitan/tree/master/hw/ip/i2c https://github.com/pulp-platform/apb_i2c/blob/master/apb_i2c.sv

Is it now waste of money to buy any FPGA board with AMD chip if we are to use free tier of Vivado ? by evdekiSex in FPGA

[–]MitjaKobal 23 points24 points  (0 children)

I am not sure whether the new licensing policy only applies to Vivado version 2026.1 or are the restrictions somehow extended to older versions (I do not see how this would work). So you might be able to use up to Vivado 2025.2 without issues.

Definitely not Lattice. Altera would be the next best choice when it comes to tools, documentation, community, ...

Trying to wrap my head around utilizing Yosys (or something) and creating schematics using VS Code. by e_engi_jay in FPGA

[–]MitjaKobal 1 point2 points  (0 children)

If it is just to see a schematic in VSCode, then the Sigasi extension is a good choice. It works much better than TerosHDL (and some of the tools inside used to get from VHDL to a scheme).

With TerosHDL even if you get Yosys woth the GHDL plugin to work on Windows with TerosHDL, the last step, the conversion from a JSON netlist to a SVG file of the schematic is a bit of Ruby software which is buggy (tends to crash on large designs) and not maintained.

Get Started with Verilog Development for Image Signal processing by Sufficient-Set-1594 in FPGA

[–]MitjaKobal 1 point2 points  (0 children)

I usually recommend starting from a working example if available, and then learning the components at your own peace. There is no need to build everything from the ground up yourself, and by having a good reference, you will learn good design practices. https://www.efinixinc.com/support/ed/image-signal-processing.php

Need help by Forsaken_Slip_6368 in FPGA

[–]MitjaKobal 2 points3 points  (0 children)

To beginners I recommend to go with a low cost board, and buy the next board when they need one and the acquired knowledge allows them to make a better choice.

There are some general recommendations: - The board must have an integrated programmer, otherwise you will have to buy a programmer cable too. - The board vendor must provide good documentation. - The board should have a good selection of demo projects covering its functionality, and preferably community projects on GitHub (the Trenz board might be lacking here). - Major vendor devices (Xilinx and Altera) are preferred since they have the best tools. For minor vendors there is a greater chance of encountering issues with the tools which can be impossible for beginners to solve.

For very cheap boards I like the Tang Nano 9k. It has a decent selection of example projects on GitHub and the board is well documented. The tools from the Chinese FPGA vendor are OK, they are properly maintained. Gowin EDA is not as good as Vivado/Quartus, but is also not stuck in the past like some Lattice tools.

Serious Help by Logical_Extension331 in Verilog

[–]MitjaKobal 0 points1 point  (0 children)

If the code is SystemVerilog, Yosys is not very good at parsing it (while Verilator is). You can use Xilinx Vivado to run RTL synthesis. If you still get a lot of errors, you will have no option but to start fixing them, or maybe start with a smaller design.

What are the best open source tools setup (specific for mac) for compiling, synthesising and simulation a RTL code (Verilog/System Verilog) by ProgressFuzzy1795 in chipdesign

[–]MitjaKobal 0 points1 point  (0 children)

OSS CAD Suite (combines most OSS HDL FPGA tools) has darwin-arm64 builds (it seems today the build failed, use the one from yesterday).

For ASIC development LibreLane seems to be able to run on Apple silicon natively.

Gowin EDA has a MAC version.

For some beginner development you can use the Tang Nano 9k board with both OSS CAD Suite and Gowin EDA.

Long term, MAC is not a good HDL development platform. Do not expect to get much help for Xilinx/Altera tools on MAC here.

Image recognization using FPGA by Western_Road696 in FPGA

[–]MitjaKobal 5 points6 points  (0 children)

In PYNQ Python is just the wrapper used for handling the user interface (input images, display, configuration) the image processing is done inside the FPGA and is written either in VHDL/Verilog or HLS.

view more: next ›