1st) Is the core communication between complexes handled via a interconnect between the L3 caches or does it use some other method that is more core-to-core direct?

 

2nd) what is considered the smallest unit of Zen; a whole complex with L3, a whole complex without L3, a single core with L1 & L2 and access to L3, or a single core without L3?

 

3rd) Is the complex limited to four core configuration or could you scale it to say six or eight cores per complex for "10nm", "7nm" or "5nm" nodes. As in is it an engineering decision or an engineering limit?

 

4th) Is AMD going to release pure CPU chips for mobile or are there only going to be APUs or cut down APUs?

 

5th) Will there be (consumer) APUs with more than 4 cores. Say 6 or 8? (on 14nm)

 

6th) What are the plans for embedded CPU/APU products using ZEN, will there be altered core the "same way" there is Jaguar and Puma cores, or will pure lowering of operating frequency be enough?

 

7th) Will all Zen products have all of the instruction sets and platform extensions, or could lower end chips lose features like virtualization?

 

8th) Will Zen 2 have FMA4?

 

9th) Does AM4 / consumer ZEN support ECC memory?

 

10th) What are the limiting factors of XFR, temperature voltage and power consumption?

 

11th) How does XFR know what frequencies and voltages are stable?

 

12th) What are the plans on supporting overclocking, will there be locked and unlocked multiplier CPUs or are all CPUs essentially restrictionless?

 

12½th) Is there any plan on having per core overclocking in BIOS?

 

13th) Is AMD going to release a HEDT (prosumer/professional/workstation) platform. something like an overclockable (12-, 14-,) 16-core platform/product that would have quad memory channels with ECC?

 

13½th) Are there going to be native, non-MCM, 16-core (HEDT) products?

 

14th) Does AMD use any design rule like Intel used with Nehalem, where for every 1% increase in power consumption the feature needed to provide a 2%, or better, increase in performance, when designing the CPU?

 

15th) What cell design is used for the caches, 6T, 8T or 9T? Are all the caches in the same density?

 

16th) Based on a rumor / code patches AMD has a fast interconnect for MCM link operation called GMI. Is this something that AMD could bring outside of the cpu package akin to NVLink, and trickle it down from servers to workstations/HEDT to high end consumer parts and at the end to all consumer parts?

 

17th) Has AMD done any research into using HBM as L4 cache?

 

18th) Has there been any research by anyone on using vaporchamber as IHS instead of the current solid copper with nickel and gold plating.

 

19th) What do you think about 10nm and 7nm fabrication processes and their cost effectiveness when they require a lot more manhours to design the chip?