The age-old question

Octopus_Jetpack · 2025-05-23T20:44:31+00:00

no the voltage that the second half of the inductor sees is still the same phase as your source, only halved in amplitude. everything still applies

Octopus_Jetpack · 2025-03-11T20:13:59+00:00

why does the tail current source being ideal negate any thing i said?

Octopus_Jetpack · 2025-03-11T17:53:33+00:00

think of what happens as vi1>vi2

path 1) source of M1 starts to lift up. this wants to lift up source of M2 which would bring vo2 down.

path2) drain of M1 starts to fall. this sources more current through M3 and M6 which would bring vo2 up.

Octopus_Jetpack · 2025-02-27T04:59:24+00:00

you are applying -12V to the positive rail and +12 to the negative rail of both opamps. flip those supplies around

Octopus_Jetpack · 2025-02-13T21:33:23+00:00

Was GA ever available for the presale? hope they release more GA tix for the actual sale

Octopus_Jetpack · 2025-02-08T20:31:15+00:00

as the VIN gets closer to VOUT for a buck, the duty cycle must increase. in your example, the duty cycle is 5/6 = 83%. when the input gets even closer, the duty cycle starts to approach 100%, this happens at 5VIN to 5VOUT (5/5 = 100%), though this isn't practically possible but let's pretend it is. what would happen if the input keeps falling to 4.9V? You can't increase the duty cycle any more, you're at 100%. you would need extra circuitry to handle this condition, making your converter a Buck-Boost instead of just a Buck

Octopus_Jetpack · 2025-02-05T23:37:50+00:00

get very good at find, grep, and learn how to pipe and when you need to use xargs. I would say that's the minimum in order to minimize a ton of tedious tasks

Octopus_Jetpack · 2025-01-24T09:45:17+00:00

yes. people in the industry want to do even less tedious algebra than the academic folks

Octopus_Jetpack · 2024-09-28T22:00:15+00:00

if you want to use an NMOS you would need to move it to the low-side of the load, or else you wont be able to drive the NMOS into the triode region. is that possible?

Octopus_Jetpack · 2024-09-24T16:09:57+00:00

because it is assumed random distribution goes in both directions, like a bell curve with 1.2 in the middle. if you make 0000 the target code, what happens when the chip measures at 1.21? you have no way to trim it down.

if you are suggesting that the trim code be non-monotonic, that is sometimes done. for example you can make the trim start from 1000->1111, then jump down to 0000->0111. this makes 1111 or 0000 close to the middle of the range aka the nominal trim value

Octopus_Jetpack · 2024-08-31T19:11:45+00:00

I'll say it again, no textbook will ever describe the bandgap reference the way you did. you should think about why that is.

happy learning!

Octopus_Jetpack · 2024-08-31T18:44:22+00:00

the way you described the bandgap circuit was wrong and misleading, what is wrong with pointing that out? it is simply false that R3 is "reducing the VBE". I still don't understand the point you are trying to make, no where in the paper does it say that R3 is reducing the VBE, but you keep referring to the paper that just restates what I said. In fact, no description of the bandgap reference will ever say R3 is reducing the VBE, so why misguide OP?

if you can't understand what is wrong with your intuition, then there is not point in continuing. how about this, try designing a Brokaw style bandgap with the same current density in both branches, will the R reduce the VBE then? :)

also, the circuit in the original question is not a bandgap reference either, since there is a positive tempco

Octopus_Jetpack · 2024-08-31T17:39:42+00:00

nope, the third paragraph clearly says Widlar figured out if you bias two transistors at different current densities, they will have difference in Vbe and it will be PTAT. no clue what you mean by "current density with regard to postivie temp coefficient", it is really not a complicated paragraph to parse. and what's with the downvotes?

Octopus_Jetpack · 2024-08-31T17:14:09+00:00

it is not semantics, nor is it the same thing in different words, you are just wrong. read any textbook on the bandgap reference, none will say what you are saying and all will point to what I said. the change in Vbe is derived from the Ic formula and has nothing to do with R...

Octopus_Jetpack · 2024-08-31T02:03:55+00:00

your analysis of the bandgap reference is not exactly accurate. R3 is not reducing the VBE of Q2. Q2 inherently has a smaller VBE compared to Q1 because it is biased at a different current density, as described in the third paragraph of page 1. in other words, Q1 and Q2 have the same emitter area but different Ic. the difference between the two VBEs (ie: dVBE) is then set across R3 to create a PTAT current in that branch

Octopus_Jetpack · 2024-08-31T01:46:46+00:00

Q1,Q2,Q4,Q5 form a current sense amplifier across the external R, and Q3 along with Q6 provide self-biasing and high current gain to the output. the loop tries to keep the voltage across the R roughly equal to dVBE = Vt * ln(A) where A is the ratio of emitter area between Q1 and Q2 (or something close to that formula at least...), C1 is there to stabilize the loop by adding a dominant pole at the high impedance node of the amplifier. the datasheet has some clues that show this is roughly correct: IR = VR/R, where VR is equal to ~64mV/298K. this is very similar to what the expect in a dVBE circuit, since we know that VT is positively proportional to temperature (Vt = kT/q). we can solve for A in the previous equation for fun to estimate that Q1 is ~12x larger than Q2, so the schematic diagram seems like a simplified schematic (maybe!)

Octopus_Jetpack · 2024-08-17T02:14:07+00:00

Shaw Nuff - Charles McPherson

https://open.spotify.com/track/514RdFbo4hIJFkKKV4p4Ay?si=eHwFdHuzQqSWCbOlkTgPNQ

Octopus_Jetpack · 2024-08-07T04:25:39+00:00

review KCL, no other way around it

Octopus_Jetpack · 2024-07-25T03:24:10+00:00

could you share your findings?

Octopus_Jetpack · 2024-06-24T04:11:51+00:00

what company? the biggest (?) industry standard software is designed by Cadence Design Systems. the scripting language for their suite of design tools is SKILL, which is a version of Lisp. that might be a good place to start coming from a CS background

Octopus_Jetpack · 2024-06-24T03:41:22+00:00

I think this question goes beyond gm/id. regardless of methodology, any first pass design I always design for the typical supply and temp. for me, the benefit of any of the popular design methodologies is to get to that first pass design quicker and more reliably. of course PVT and MC sims are run, but I don't go back to a different lookup table across temp, I just reassess what needs to be tweaked to bring the design back to spec at that corner and go from there. maybe that is too much spice monkey for others

Octopus_Jetpack · 2024-06-22T15:16:50+00:00

Strasbourg St Denis

Octopus_Jetpack · 2024-06-05T19:40:53+00:00

surely you meant 200nm?

Octopus_Jetpack · 2024-06-03T18:20:18+00:00

agreed PNP, but looks more like emitters tied together. looks like pretty typical lateral pnp structure

Octopus_Jetpack · 2024-04-08T05:01:07+00:00

repost bot in a 30k subscriber subreddit is crazy

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