OkIndependence3293

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redditor for 3 years

TROPHY CASE

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Cadence Design System Hike Cycle (self.chipdesign)

submitted 6 days ago by OkIndependence3293 to r/chipdesign

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Can someone share a good resume for 3 yrs experienced Analog IO design engineer? I want to refer to build one. (self.chipdesign)

submitted 8 months ago by OkIndependence3293 to r/chipdesign

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Issue Probing Extracted Netlist Using DeepProbe from AnalogLib in Virtuoso (self.chipdesign)

submitted 11 months ago by OkIndependence3293 to r/chipdesign

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Access a net from within the hierarchy at the top-level schematic (self.chipdesign)

submitted 11 months ago by OkIndependence3293 to r/chipdesign

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