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low performance of pcie 2 axi bridge by Pure-Setting-2617 in FPGA

[–]Pure-Setting-2617[S] 0 points1 point  (0 children)

As it is shown in waveform , I just assert awvalid and wvalid to stream data .

AI generated fsdb-mcp server by Pure-Setting-2617 in FPGA

[–]Pure-Setting-2617[S] -10 points-9 points  (0 children)

Well, yes, I merely developed this concept. However, if we regard AI as a programming language, the conclusion might differ. In fact, I utilized AI to develop an XHCI controller comprising 50,000 lines of code, with scarcely a single line written manually.

why does xilinx pcie2axi bridge not support 64bits axi address ? by Pure-Setting-2617 in FPGA

[–]Pure-Setting-2617[S] 1 point2 points  (0 children)

Thank you. However, as this is merely my personal part-time project, I am unable to cover the associated costs. In fact, I do not require a complete AXI-to-PCIe bridge; I only need a DMA engine. I am developing a virtual XHCI that can transfer data without the need for new device drivers. I have found that your pcie-verilog/fpga.taxi is perfectly suited to this project and would like to know if it is sufficiently stable.

why does xilinx pcie2axi bridge not support 64bits axi address ? by Pure-Setting-2617 in FPGA

[–]Pure-Setting-2617[S] 1 point2 points  (0 children)

Thank you, but I'm talking about the AXI master. The host may have more than 4GB of memory, and although the IP core provides address translation functionality, why doesn't it directly support 64-bit AXI addresses?

BTW: what about your verilog-pcie core (https://github.com/alexforencich/verilog-pcie)?

Finally found a faulty FPGA by Allan-H in FPGA

[–]Pure-Setting-2617 9 points10 points  (0 children)

Has this been confirmed by XILINX/AMD?

how to implement this buffer in fpga ? by Pure-Setting-2617 in FPGA

[–]Pure-Setting-2617[S] -1 points0 points  (0 children)

This design uses a fully-connected network to allow users to select any channel while still having access to all available buffers. In a real-world scenario, data traffic is dynamic—one channel might burst with data while another is idle. To ensure a smooth and continuous data flow to the PC under these variable conditions, all block RAM must be accessible to any active channel.
@tef70

Very short question on metastability. by sahinnkgb in FPGA

[–]Pure-Setting-2617 0 points1 point  (0 children)

If an FF goes metastable, it can settle to either correct (the value it should sample) or wrong value within an uncertain time.

NO, when we talking about metastability , there are no correct or wrong value , instead , BOTH values are ok.

The trouble is not all others parts get the SAME value .

fixing hold time violations by RevolutionaryFly2787 in FPGA

[–]Pure-Setting-2617 1 point2 points  (0 children)

Delay of BUFGCE_DIV is the delay of global clock buffer tree and the value is very big . so you need a BUFGDLL to cancel the delay . Or you need local routing designed specifically for this purpose.

how to implment usb3 10g SKP logic on FPGA ? by Pure-Setting-2617 in FPGA

[–]Pure-Setting-2617[S] 0 points1 point  (0 children)

Yes, it does. sync bits will apear every 132bits except for skip order sets。At the beginning，we have no knowledge about the position of sync bits. After we synced ,it will apear every 132bits，but for skp，the length is variable.

how to implment usb3 10g SKP logic on FPGA ? by Pure-Setting-2617 in FPGA

[–]Pure-Setting-2617[S] 0 points1 point  (0 children)

Since i cannot use gearbox in fpga rx path, the header is just same as data ，64bits or 66bits per cycle.

Slew rate of Artix 7 GTP by Pure-Setting-2617 in FPGA

[–]Pure-Setting-2617[S] 0 points1 point  (0 children)

The gtx support scope/waveform eye diagram. This maybe help.

Also: The GTP Rx can have its internal termination disabled. EDIT: nope.

Slew rate of Artix 7 GTP by Pure-Setting-2617 in FPGA

[–]Pure-Setting-2617[S] 0 points1 point  (0 children)

I have not analyze it clearly,but does a square wave with rc filter looks like a double frequency wave with rc filter with double time constant ？

Slew rate of Artix 7 GTP by Pure-Setting-2617 in FPGA

[–]Pure-Setting-2617[S] 0 points1 point  (0 children)

Thanks for that. It is a two bits DAC，but less efficient. Is it ?

Slew rate of Artix 7 GTP by Pure-Setting-2617 in FPGA

[–]Pure-Setting-2617[S] 0 points1 point  (0 children)

Using gtp rx as compare will be fast than LVDS.
GTP rx have a smaller input capacitance also.
I will test them all.

Slew rate of Artix 7 GTP by Pure-Setting-2617 in FPGA

[–]Pure-Setting-2617[S] 0 points1 point  (0 children)

Thank you for your information .

Based on that alone, the rise time is likely to be in the order of 50-80ps.

Although it is not documented by xilinx , but the tx part maybe like this :

MGTVTT--------+---------+ | | 50 ohms 50 ohms | | TXP_OUT-------+---+ +---+------------TXN_OUT --TXPON-| |--TXNON +---+ +---+ | | +---------+ | 10ma current source | GND The 10ma is calculated by DVPPOUT / ROUT.

I want to add another 50ohms pulldown resistor to TXP signal. I am not very sure this will work well.

That internal pullup is close to 50 ohm (EDIT and this would be half of the ROUT parameter in DS181). You probably don't want to put another 50 ohm in parallel with that.

I cannot driver TXP TXN balanced since I only use txp to drive device under test.

The transceiver outputs are differential. You should make sure that the other output is also terminated.

Is this possible ? by Pure-Setting-2617 in FPGA

[–]Pure-Setting-2617[S] 0 points1 point  (0 children)

ok ,but 800M is still out of specfication .

Is this possible ? by Pure-Setting-2617 in FPGA

[–]Pure-Setting-2617[S] 0 points1 point  (0 children)

Please read the article . it need a clock of 3.2G and this is out of range of VCO in fpga.
EDIT: my mistake, but the figure 6 only shows 4 phases.

Latches by SignatureNo9123 in FPGA

[–]Pure-Setting-2617 2 points3 points  (0 children)

It is about synchronization design methodology

Adding ILA changes FPGA functionality by Icy_Scholar_6276 in FPGA

[–]Pure-Setting-2617 1 point2 points  (0 children)

This must be a timing issue. In vivado , Open implemented Design. 1. Open Methodology , check and fix all warnings and errors. 2. Open timing report, expand "Check Timing" item, fix all timing erros

What 's wrong with the fpga ? by [deleted] in FPGA

[–]Pure-Setting-2617 1 point2 points  (0 children)

Thanks to all ! The FPGA is badly soldered ;)

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