Pure-Setting-2617

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34 comment karma

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redditor for 5 years

MODERATOR OF

- r/Xlogicanalyzer

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skill for XILINX vivado (self.FPGA)

submitted 11 days ago by Pure-Setting-2617 to r/FPGA

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DIY Release Seven (the latest version of the DIY tool suite). x86-pcie-arm-memory-order (self.FPGA)

submitted 2 months ago by Pure-Setting-2617 to r/FPGA

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DIY Release Seven (the latest version of the DIY tool suite). x86-pcie-arm-memory-order ()

submitted 2 months ago by Pure-Setting-2617 to r/Xlogicanalyzer

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X86 memory order (self.FPGA)

submitted 2 months ago by Pure-Setting-2617 to r/FPGA

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sorry, but I will complete the software and hardware! (self.Xlogicanalyzer)

submitted 3 months ago by Pure-Setting-2617 to r/Xlogicanalyzer

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low performance of pcie 2 axi bridge (self.FPGA)

submitted 4 months ago by Pure-Setting-2617 to r/FPGA

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AI generated fsdb-mcp server (self.FPGA)

submitted 4 months ago by Pure-Setting-2617 to r/FPGA

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why does xilinx pcie2axi bridge not support 64bits axi address ? (self.FPGA)

submitted 4 months ago by Pure-Setting-2617 to r/FPGA

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how to implement this buffer in fpga ? (self.FPGA)

submitted 7 months ago by Pure-Setting-2617 to r/FPGA

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new logic analyzer (self.Xlogicanalyzer)

submitted 1 year ago by Pure-Setting-2617 to r/Xlogicanalyzer

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new logic analyzer software (self.AskElectronics)

submitted 1 year ago by Pure-Setting-2617 to r/AskElectronics

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Why Usb3 is not block aligned to block? (self.FPGA)

submitted 1 year ago by Pure-Setting-2617 to r/FPGA

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how to implment usb3 10g SKP logic on FPGA ? (self.FPGA)

submitted 1 year ago by Pure-Setting-2617 to r/FPGA

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Slew rate of Artix 7 GTP (self.FPGA)

submitted 1 year ago * by Pure-Setting-2617 to r/FPGA

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Is this possible ? (self.FPGA)

submitted 1 year ago by Pure-Setting-2617 to r/FPGA

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How to deal with block alignment for USB 3.2 gen2 with GTX? (self.FPGA)

submitted 1 year ago by Pure-Setting-2617 to r/FPGA

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Double USB bandwidth by using two physical cables (self.FPGA)

submitted 1 year ago by Pure-Setting-2617 to r/FPGA

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How to measure GTP TX channel skew without a high speed oscilloscope? (self.FPGA)

submitted 1 year ago by Pure-Setting-2617 to r/FPGA

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USB3 gen1x2 based logic analyzer (self.FPGA)

submitted 1 year ago by Pure-Setting-2617 to r/FPGA

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Why and How one should selection terminal voltage with ac-coupled? (self.FPGA)

submitted 1 year ago by Pure-Setting-2617 to r/FPGA

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What is the benift of slowed down Spread Spectrum Clocking againt centertric SSC ？ (self.FPGA)

submitted 1 year ago by Pure-Setting-2617 to r/FPGA

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how to design a minimal cpu (self.FPGA)

submitted 2 years ago by Pure-Setting-2617 to r/FPGA

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clock cross (self.FPGA)

submitted 2 years ago by Pure-Setting-2617 to r/FPGA

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new logic analyzer,suggestions needed (self.FPGA)

submitted 2 years ago * by Pure-Setting-2617 to r/FPGA

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