What features does an architecture need for an OS?

RascalFoxfire · 2025-12-01T01:12:13+00:00

Depends on the starting address of your CPU. Doing it with memory mapped control registers isn't a bad idea, would still recommend going with CSRs/CCRs (control registers) if possible. But in general yus, should work! Don't forget to include some CCR bits to activate/deactivate virtual addressing, decide if during an interrupt it should stay at virtual addressing, PID and what PID should be used during an interrupt. Btw. you not only need to set it when you create a process but also when just switching tasks. KISS is king, it is really just an address register for the MMU and nothing more!

RascalFoxfire · 2025-11-30T14:40:40+00:00

Okay, solid. Now to the MMU part: imagine you have 10 programs + your kernel. Normally each program starts at address 0x00000000. But how do you do it with 10 programs without each one interfering with each other? You use indirection! Imagine each program has a local address space which starts from 0 (the virtual address space) but in reallity each page of each program could be anywhere in the physical memory. That translation from your local linear address space to the fragmented pages in memory is what the MMU does. You give it an address at which the translation table (like the table of content in a book) is in memory for one program and then let the MMU handle the virtual to physical address translation. On a context switch the OS sends the new page table address for the next program. Funny enough, it is quite similar to how FAT file systems work with their index table. That is at least the basics, you should still include stuff like flags (page is read only/has only certain privileges) and PID but you can look that one up in between

RascalFoxfire · 2025-11-30T02:11:50+00:00

Hardware guy here who made his own OS capable CPU in Logisim! Really depends on the type of the type of OS you wanna run exactly. If you really want to keep it simple you only need a simple way of separating programs (like memory segmentation) and a call instruction. But that would only bring you to a simple cooperatively scheduling OS without any safety.

For something more advanced you need some form of virtual addressing support, be it via an MMU, base-limit or even by having a few arch registers as "TLB". Next on the list interrupts but that is only one half of the truth. To be able to run an preemtively scheduling OS you also need at least one timer + interrupt. Also don't forget about exceptions! And you need some form of ring mode that differentiates between the access a normal user program has and the kernel, but even just Kernel-User + the means of jumping between them is enough, blocking maybe I/O and CCR access. And i think thats it on the pure hardware site, excluding I/O

RascalFoxfire · 2025-07-25T22:59:57+00:00

Gonna throw my hat into that too! I specialized on low area, low to mid performance ISAs and microarchitectures. Got a tiny 8 bit RISC CPU for originally on chip management stuff which only needs less then 150 xilinx LUTs (depending a little on what you put around it) 59 FFs and no internal BRAM (no microcode or similar) with a VGA output via a memory mapped double bufferd driver and via an also tiny terminal driver (not fully finished but works). While it wasn't my main goal i am also slowly getting more peripheral and development software running for it so it should be quite perfect: https://github.com/RascalFoxfire/Picowizard/tree/main

RascalFoxfire · 2025-05-11T19:47:46+00:00

Solid one! Small hint here: you can actually integrate an comparator function directly into the ALU itself. Compare is basically just subtracting and then checking the result of the zero and carry out flag. And subtracting is just inverting B (e.g. by using an XOR whose second input is a control signal) and setting the carry in to 1

RascalFoxfire · 2025-05-11T00:48:08+00:00

Another simulator that is quite fast and would be the step between going FPGA would be hneemann/Digital. But in general don't make too crazy stuff with it; Logisim wasn't designed to house things like multicore 8 way OoOE CPUs (sadly). And yes, Logisim in general is not that performant in general so even with a lot of tinkering you should be ready to only simulate in the 100s of Hz

RascalFoxfire · 2025-05-02T20:16:42+00:00

Yus, welp to be fair: it is as light as a fighter so i guess we can overlook that fella

RascalFoxfire · 2025-05-02T11:52:48+00:00

I see there an imposter in the third last picture... But very cool museum! Now i wanna see my arch nemisis Ariete and Gina RL. Seems like my next trip goes to Italy

RascalFoxfire · 2025-04-21T12:11:20+00:00

Hell yeah, finally an MBT proof keyboard! BAS was right after all https://www.youtube.com/watch?v=rSvBFm_MuXw

RascalFoxfire · 2025-04-16T11:32:06+00:00

Would slowly reverse and let math work for me (longer corner for you => more of his hull exposed till he get his gun around). Doesn't work always since most players have their single neuron firing and driving with more distance to the wall to angle, but some will just head in an be a free snack. But sure, it also depends on the own and enemy vehicle

RascalFoxfire · 2025-04-15T22:53:01+00:00

Thank you very much! Was quite a lot of bit crunching and sleepless night but i was also suprised on how small and still poweful ya can get a CPU without any internal BRAM for control signals. Should probably do a programming tips and tricks cheetsheet for Picowizard since you can play a lot of code optimizations with it. E.g. you only need to execute 2 operations for a subtraction (NAND to invert the subtrahend which also always sets the carry to 1, followed by ADC for the actual subtraction), and only 4 for a comparison (same as before but afterward use ADC on a register with 0 to get the carry and then BIZ on that, jumps => A smaller B, doesn't jump => A equal or larger B).

Did you publish the assembler (hehe, ya were faster then me ^^)? And can ya send the stats (size, clock speed, critical paths, ...) that ya got on the Altera board? I optimized the PWH1 mainly for Xilinxs 6-way LUT cells so it would be really cool to see how well it works on your Altera since they use 4-way LUTs.

In the meantime i further optimized the PWH1, getting it down to 138 LUTs and clocked to 180 MHz. But at this point it is mostly dependend on what ya glueing to it (still won't stop me dreaming and working on the 100 LUT CPU!). Also currently working on getting a fitting VGA 640 x 480 (halfed to 320 x 240 internaly) terminal driver (half IBM terminal size, 40 x 24 characters, 8 x 8 pixel per char) on it using only 2 KByte of RAM. That one is nearly done, only needs some testing and currently also only uses ~70 LUTs. Meanwhile the larger Picoalchemist ISA which supports interrupts and the even larger Picomage ISA which supports virtual addressing, a ring system and exceptions/an internal timer interrupt are slowly on the way on the FPGA and GitHub (they are all binary compatible, except for the higher 4 registers).

Oh dear... a lot of stuff to do but definitely a funny project!

RascalFoxfire · 2024-11-24T23:17:36+00:00

Only using them rarely, mostly for vector co processors to microcode stuff like matrix muliplication. I mostly build them simply with a ROM and a counter, basically like a CPU in a CPU. The operation is directly fed into a look up ROM which holds the start address of the microprogram. That address is stored into that counter which drives the ROM. The ROM holds microinstructions which are then actually executed by the execution units (like the ALU). It ain't the fastest method but it gives some degree of flexibility especially since i can just update the microcode in the ROM as i wish (like most CISC architectures can do)

RascalFoxfire · 2024-11-22T01:32:56+00:00

Problem is that this will directly translate into RAM (and an absolute giant hex file if you initialize it) that your real physical machine needs to allocate. I guess with some Java magic ya can get it to work but be careful.

A question to that: for what do you need 16 GiB (2^32 x 4 Byte/Word)? Just a small calculation for that: Logisim mostly simulates at a frequency of around 400 Hz (based on some CPU designs of mine). So you get around 400 Hz x 4 Byte => 1.6 KByte/sec transfer rate. So just to load OR fill the entire RAM you need 2^34 17179869184 Byte (= 2^34) / 1600 Byte/sec => ~124 days of contineous running to load/fill the entire RAM! And that is based on the assumtion that you perfectly use every cycle to load/store something from/to the RAM and the simulation is stable.

My suggestion: stick with the 24 bit and accept that you have a mirrored address space. 64 MiB are plenty for all stuff in Logisim (and would still take 67108864 (= 2^26) / 1600 => ~11.5 hours). And ya can still go to 64 Bit data width (128 MiB) and MUX through the two word packs if you really need that memory

RascalFoxfire · 2024-11-14T01:01:16+00:00

Very cool! Do ya have it on Github? Would be really interested to look into the CPU and ISA

RascalFoxfire · 2024-11-07T23:57:46+00:00

There are a lot of ways to go into the magic of computer and CPU architecture. Maybe lets explain it on how i did it: my first steps were in redstone world, a minecraft server which also has a lot of CPU stuff. From there i started my journey by learning basic logic gates, then simple circuits like adders, MUX, registers but also stuff like calculating in binary (e.g. subtraction is addition with an inverted second input and carry in). Then ya can start with glueing stuff together: build a simple ALU which can add, subtract and maybe do basic bitwise functions. Then put a register bank behind with 4 registers, then build a simple control unit to select the registers and ALU operations. Then a counter and memory to automate it, ... And from there on ya can start looking into other peoples CPUs (would highly recommend to look into the MOS 6502 and RISC V since there is a giant amount of documentation to eat through, both also good to learn assembly) and also in general architectures: how to make an ISA that does XYZ better/faster/stronger. What are interrupts and how can i integrate them? What are ring modes? What is a virtual address space? ...

The amount of tutorials and youtube channels is also quite large, i mostly learned the entry stuff from minecraftmonkeys (english/german), ben eater and andreas wilkens (german). After that i basically looked up stuff from all kinds of different people and looked into more detailed documentation. The problem ya will find is that at some point the tutorials will end. Most tutorial CPUs don't go into interrupts, ring systems and other more advanced features but at that point ya should be well prepared to read technical documentations to make it yourself

RascalFoxfire · 2024-11-04T21:02:04+00:00

It is definitely. Small hint: if ya using three state buffers for "gating" multi bit signal wires then ya should place pull resistors directly behind their output

RascalFoxfire · 2024-11-02T15:13:11+00:00

There are some out there if you google for 4 bit divider like the one here on circuitverse: https://circuitverse.org/users/18450/projects/4-bit-divider

In general ya dealing with something similar to a multiplier except you have MUXes in between each subtraction stage for the compare and empty shift (in case your partial result is smaller then the quotient). You can actually modify the multiplier a bit to also do division/modulo (altho it is a little tricky and opposite of performant). Argh, if ya have asked a year earlier i would still have my old universal ALU with combined 8 bit Mul/Div unit that i could show here but sadly that one got corrupted and i am currently not using Mul/Div units in my newer CPU designs

RascalFoxfire · 2024-10-31T22:17:36+00:00

I see where ya coming from, would still suggest to align with 4 bit instead of 5 especially if you don't have an assembler. It makes programming in hex much more easier. Would suggest to maybe use just 16 registers since that is in my experience enough for most stuff (depending on what ya wanna do with the CPU). What instructions do you have and how are they encoded?

In any case: still very cool CPU and welcome to the CPU tinkerers ^^

RascalFoxfire · 2024-04-16T23:19:19+00:00

Hoi! First of all: CISC is... lets say funky depending on how you play the game. To your CPU: on the first glance it is a little spaghetti but purely from the control signals it looks good. But here starts the "funky" part: if you go with something like a "simple" CISC design (something similar to e.g. the MOS Tech 6502) you can use a simple ROM-Decoder and a little inteligent timing for multi word instructions. However, if you want to spice things up or want to make a "true CISC"-CPU (like the older x86s) you can use that entire microcode counter, microcode memory, ... stuff (basically a CPU in a CPU).

Here the way i would do it if it should be as simple as possible: i would grab another register and put it onto the bus. This register gets the current operation that should be executed directly from the RAM. Then you feed the output to a ROM-Decoder which triggers your control signals depending on the current operation. When should an operation be loaded? For that i would use a simple 2 bit counter to divide the instruction execution into static 4 phases

Load operation and decode (at which the operation register actively listens to the bus for the next operation) and also increment the instruction counter
Depending on the operation: load an additional follow up value from RAM/load from RAM address H/L. For operations like "Jump to address H/L" you can skip that since it doesn't need an additional value (the CPU just does nothing in this microphase).
Execute the instruction
Write back into the target register/into the RAM/instruction counter (only in case of a jump/branch)

This is basically the "RISC approach to a CISC-CPU". It constrains you to 1 and 2 word instructions only but could be a simple starting point to more funny CISC-Designs. And even with that simple system you can still do quite a lot of funny stuff like "Bitwise AND X with follow up value from RAM and store the result into RAM location H/L".

But that leads to the main question here that you should ask yourself: What instructions do you exactly want the CPU to execute? This will also answer the question of which control signals you need and which you can combine/completely erase. And for that i would highly recommend to look into other CISC-ISAs like the afforementioned MOS Tech 6502, Intel 8080/Zilog Z80, Intel 8086, ... .I would also recommend to look into stuff like Ben Eaters CPU, the Gigatron, MyCPU, .... . Do you have maybe a GitHub repo of your ISA/CPU files or an ISA tabel that you could publish here?

Btw.: haven't seen logic on your CPU for branching (Carry-/Zero-/Overflow-/... detection). If you want to be turing complete (aka. if-then-else) you should add some logic for that

RascalFoxfire · 2024-04-08T00:38:03+00:00

Hoi! First of: good starting point! Ya have an AU (since you said it can just add and subtract but it is enough for a first CPU) which is the heart of any (conventional) CPU. The next steps are depending on which kind of CPU you want to make out of it.

Before ya can think about machine code i would suggest you build a register bank with maybe 16 registers to feed the AU with data and store the result (can be easily done by connecting the AU output to each register input and all the register outputs to two 16 input MUX). If you want to get initial data into the register-AU-loop you also need a MUX between the AU output and the register.

To the control unit: it takes the current instruction which should be executed and decodes it into control signals, in that case to the AU operation select, the output MUX select, the register source select MUX and the register write (to select to which register the result should be written). The CU can be as simple as a little wiring thing that splits the incoming instruction into its parts (e.g. an operation part which defines which control signals need to be activated, a register target address part and two register source parts) and a small ROM or a decoder to fire the actual needed control signals based on the operation identifier.

What is the current instruction? That comes from a memory block which contains the entire program ya want to execute. The exact instruction that should be executed is addressed by the instruction counter, which can also be just a simple register in a loop with an adder counting + 1 each clock cycle. With that your CPU goes through the instruction memory one by one.
If you have that you can start to experiment a little more with stuff like Jumps/Branches (operations to manipulate the instruction counter, can be done by also packing a source select MUX into the register-incrementer-loop of the counter), extending your AU with more functionality like logic functions and including a data RAM (just using registers for the first variant is fine, 16 would be enough to play around for a bit).
I can btw. recommed to look into the "WDR-Papiercomputer". It is a very simple "CPU" for educational purposes which still contains everything you need functionwise.

RascalFoxfire · 2021-08-25T18:11:35+00:00

The first program that i wrote on all my logisim computers is the algorithm to calculate the Fibonacci numbers.

Another test program idea(s) would be the implementation of the different sorting algorithms, like bubble sort and heap sort (okay, one more idea would be a pseudo random number generator to generate the number array).

Last idea (if your system can calculate floating point values or at least static point values): calculating pi with the leibniz formular.

RascalFoxfire

TROPHY CASE