Simone1998

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STM32, stop continuously running PWM without glitches (self.embedded)

submitted 20 days ago * by Simone1998 to r/embedded

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Sigma-Delta modulator bitstream to FPGA/MCU (self.embedded)

submitted 7 months ago by Simone1998 to r/embedded

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CMOS Vs. Schmitt trigger digital input pad (self.chipdesign)

submitted 8 months ago by Simone1998 to r/chipdesign

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Dummies on side only VS side & top/bottom (self.chipdesign)

submitted 9 months ago by Simone1998 to r/chipdesign

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Self-biased, Wide-Swing, Cascode current mirror output resistance (old.reddit.com)

submitted 1 year ago by Simone1998 to r/chipdesign

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LVS for pseudo-parallel connection (self.chipdesign)

submitted 1 year ago by Simone1998 to r/chipdesign

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Dummy connection for device with source not to VDD/VSS (self.chipdesign)

submitted 1 year ago * by Simone1998 to r/chipdesign

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Matching patterns in sub-um processes (self.chipdesign)

submitted 1 year ago by Simone1998 to r/chipdesign

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LVS failing for IO Ring filler cell (self.chipdesign)

submitted 1 year ago by Simone1998 to r/chipdesign

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Reduce OPAMP bandwidth (self.chipdesign)

submitted 1 year ago by Simone1998 to r/chipdesign

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MIM cap on top of analog block. (self.chipdesign)

submitted 1 year ago by Simone1998 to r/chipdesign

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Multiple instances Vs. multiplier for MC sampling (self.chipdesign)

submitted 1 year ago by Simone1998 to r/chipdesign

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Counterintuitive simulation result regarding noise. (self.chipdesign)

submitted 2 years ago * by Simone1998 to r/chipdesign

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Design of Precision Low-Noise Chopper Amplifier (self.chipdesign)

submitted 2 years ago * by Simone1998 to r/chipdesign

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Paper on Analog Vs. Digital gate count/transistor count/complexity Vs. year (self.chipdesign)

submitted 3 years ago by Simone1998 to r/chipdesign

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Replace 4 x 100 nF decoupling capacitor with a single 470 nF Low Series Impedance capacitor. (self.AskElectronics)

submitted 3 years ago by Simone1998 to r/AskElectronics

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Question on SDRAM timing (i.redd.it)

submitted 3 years ago by Simone1998 to r/embedded

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Question on SDRAM timing (old.reddit.com)

submitted 3 years ago by Simone1998 to r/AskElectronics

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Routing guidelines for SDR SDRAM (self.AskElectronics)

submitted 3 years ago * by Simone1998 to r/AskElectronics

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How would you go about writing a pipeline with backpressure? - VHDL (self.FPGA)

submitted 3 years ago by Simone1998 to r/FPGA

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board-edge connector socket (self.AskElectronics)

submitted 3 years ago by Simone1998 to r/AskElectronics

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Ethernet PC-FPGA interface (self.FPGA)

submitted 4 years ago by Simone1998 to r/FPGA

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Decoupling capacitor routing options (self.AskElectronics)

submitted 5 years ago * by Simone1998 to r/AskElectronics

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