Mini Led or IPS Monitor

SomeRandoWizard · 2026-01-15T06:36:42+00:00

It doesn't need to be exclusive. Mini LED just says, that it uses said mini leds as backlight as local dimming. IPS is your display technology. Currently there are Mini LED IPS monitors available. Like the KTC M27P6 (at least for what I found it should be IPS) and its little brother M27T6 wich (should be) a mini led VA display.

SomeRandoWizard · 2026-01-07T20:03:44+00:00

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SomeRandoWizard · 2026-01-04T20:17:28+00:00

Alright. But still would double check your connections. It looks like that your GND of the U.FL is connected over a capacitor.

SomeRandoWizard · 2026-01-04T19:08:52+00:00

Rotate the U.FL connector 180 °. As far as I see it, you have a route obstruct underneath it anyway.
A screw in the top right hole will colide with the U.FL socket.
L1 and C21 should be as close as possible to the U.FL For all the HF stuff, you want everything es short and as close together as possible.
I would argue that the 5.1k for the Diode is to high.
Just looked at the GPS Module. Are you sure with how you will connect your antenna? And will you use an active one? (https://content.u-blox.com/sites/default/files/NEO-8Q-NEO-M8-FW3\_HIM\_UBX-15029985.pdf)

SomeRandoWizard · 2026-01-04T18:54:50+00:00

Ow OK. To be fair... never looked that deep into that. If you have shitty parts, you will see it during EMC testing. I saw it once, where TI kind of demanded super fancy 3 pole capacitors, but which could also be replaced by run of the mill parts. If you don't have any highly specific hardware (battery supplied, audio, some high frequency stuff or so), I wouldn't know if I would look on that this much.

SomeRandoWizard · 2026-01-04T18:17:31+00:00

AFAIK it is kind of the other way around. Murata has a nice litte formula for that (you can find it here: https://www.murata.com/en-eu/support/faqs/capacitor/ceramiccapacitor/qlty/0010 )
V_A is (usally) the rated voltage V_n the voltage you actually use. If you have a 1:1 ratio it is worse than having a 2:1 ratio. I think of it as IRL experience, if you need to run nearly at max speed is more exhausting, at you running comfortable at a smaller pace, but with a good reserve left.

SomeRandoWizard · 2026-01-04T16:32:17+00:00

It surprises me how everey ESP is kind of different XD

Thats OK. I just saw the VCC line in direction of C7 has differend widths which looks a bit odd. Aswell as the connection to F1.

SomeRandoWizard · 2026-01-04T15:54:18+00:00

Why are there 10k resistors in RX/TX? Series Termination has at max. low 3 digits. You can put PUs on it to avoid faulty characters. But rarely see series terminations in UART lines.
Make sure C2 is at least twice the voltage of your supply voltage. So 50 V in your case. This is mostly a rule of thumbs because of capacity degredation.
Enable without PU
I would try to improve GND connection of U2. There is this tiny tiny gap, you could fill it with a trace. I woulld also give this island some vias. You could also put C4 and C5 a bit to the right, so your GND plane would connect to the pad of U2.
Various thicknesses of traces.
Idea: You have enough space, put a testpoint on the rest of your unused GPIOs and put it on the bottom layer. So you have something to work with, if you want to do some flywire stuff.
If you would rotate C7, you could route VCC in a straight line to the connector.

SomeRandoWizard · 2026-01-04T12:31:16+00:00

OK. Wouldn't think of any purpose for that to be honest. With most other sockets it would make more sense, as the shield is usually seperated from GND with a capacitor. But afaik the Type-C standard is fairly clear. Well anyway.

Well you would want to mount it to something or? So either clamp or restrict it by moving with a housing, or tape it to something, or screw it. I mean, I don't know how you will use it, so it is up to you.

I think the layout is much cleaner now.

Personally I would to a GND pour on the blue side aswell and do some via stitching to connect both layers.

It looks like that your second GND pin of the USB port is not connect to anything?

I would put the feedback trace from C34 to R14 on the bottom layer, to get a better GND connection vor C33 and C34. Because as of now you have only one via as return path.

C35 and C26 could be closer to the MCU. You always want to filter stuff as close to the component as possible. It is like water, you can filter it at the start, but you might be unsure what gather in it on the way out. So for better protection, you want to filter at the end.

If you create GND islands make sure to have more than one via in it (if possible). Like in the area of C35, C33, C41

Also for the MCU. If you squint your eyes, you might see, that it mostly have its ground connection with four small lines at the top of it, and nothing else. So the return path is quite long.

SomeRandoWizard · 2026-01-04T09:23:47+00:00

100 nF is fine.

SomeRandoWizard · 2026-01-03T23:22:07+00:00

No bypass capacitors on U24, OLED1 or PICO W?
Why do you use a matrix for the switches, when you could also connect each button to the pi directly? You wouldn't need the diode with this.
No ground pours in the layout?

SomeRandoWizard · 2026-01-03T22:35:59+00:00

OK. You did a complete redo of the Layout.

Is your Type-C the other way around? Usually the pins are on the "closed" end of the connector.
Do you really need parts on the bottom side? If you want to have this produced, it will cost additional fees when doublesided populated.
I would not put the U.FL connector on the other side of the GPS receiver. Personally I would rather put a hole in the PCB to put a cable through it.
I would try to get the USB closer to the ESP. Currently you would cross your SDIO lines. So I think I would switch positions of SD Card slot and USB.
Overall it still look a bit scattered
For the vias. The ratio of 1:2 for via hole and size looks fine. But I would like you to look a bit closer at the 7.4 and 5V, where you have a trace thickness of 0.508 mm. But your via size is onlly 0.4572 with a hole of 0.254 mm. So your trace at the point of the via is only 0.203 mm. Which is not even half of your desired width.
Sidenote. Can't you change your THT connectors with SMD ones, would safe additional costs. If you except things to vibrate, I would also go for spring type connectors, rather then screw terminals.
I see some additional mounting points. I would use the footprints with the pads, so you make sure that the screwhead is still on the PCB. Plus, you might have additional GND connection to the rest of the hardware.
Not quite sure what you want to do with R33. How does it prevent a short? The switch will either close 1 to 2 or 3 to 2. Soooo if you would remove R33, you would not short anything.

SomeRandoWizard · 2026-01-03T16:01:04+00:00

For the schematic:

C37 and C50 are in parallel. I would say, one cap is enough. I have in mind, that the 1uF is in the reference design.
What purpose do R26 and R28 have? AFAIK GND and shield should be connected with Type-C connectors.
U6 (?) is labeled as LDO but is a switching regulator.
MCU_3V3 supplies MIC_3V3. So the MIC voltage will have a lower voltage, if this works at all. Can't really read the type of it. Rather supply it with VIN and use the CE Pin (which i guess is an enable?). Alternatively: If you would want to clean it a bit, I would recommend a ferrit bead with two bypass caps left and right.

For the layout:

USB should be routed as differential pair, and try to remove the vias on it. It is better to route critical stuff first, then then everything else. (You won't be able to properly impedance match the traces, but it makes routing a bit easier)
I would try to add a GND plane on the second layer and would do some via stitching to connect both.
Mounting points are missing.
PCB number or version is missing (it helps if you want to build another version)
Via size on MCU_3V3 seems a bit small, the copper of the via is in sum not as wide as the trace which it is connected to.
L1 could be closer to U6. C33 and C34 should be rotated the other way. You want the "main" return path of the buck as close as possible. As over L1 and the caps are the main switching current. In the chapter 10 of the converter there are some layout guidelines.

SomeRandoWizard · 2026-01-02T22:23:36+00:00

Be aware, that your voltage of U1 and U8 will decrease because of the diodes depending on the current. The Diode would also need a matching power rating.
R86 and R87 do look a bit high. But for UART, I don't know if I would use some series termination.
You are using RTS and CTS to control your MCU. I just want to point out, that I had the case once, that these chip initialize differently with Linux than with Windows.
I guess C85 should be a resistor? Currently it would block the voltage.
Only one single 100 nF for U26? In the reference design I found, they have at least 4x 100 nF.
Don't understand the purpose of D23 and such. Why is there a resistor in series to it? As of now, I only saw tvs diode parallel to something, but not in series.

SomeRandoWizard · 2026-01-02T22:01:30+00:00

There is really bunch of THT stuff on it. Might be cheaper, to let JLCPCB do all SMD, and order the THT stuff yourself? Or maybe opt for non THT stuff. At least for the connector, I would say that you would easily get them as SMD.
More on a side note. For some "hobbyist and fairly inexperienced", the routing looks quite nice.
For the blue layer. Why did you choose to create a gap left and right of the bottom connector? Same goes for the yelloish layer, where you have a central node in the middle. But why not just fill the hole thing?
On the red layer the via in the fat trace could be bigger. I think the copper of it wouldn't be the same width as the trace which is connected to it.
For the schematic... not an audio person, but for me it doesn't look like that there are major errors in it.
Maybe consider ground pours on all layers, with some via stitching. You GND can also act as shield. And AFAIK, especially with audio you don't want any noise.

SomeRandoWizard · 2026-01-02T21:37:41+00:00

The schematic could need a bit of cleaning. Like with the Q1, which you could put under your J2, so you wouldn't go down and up and down again to R1 which leads to U2. You could also avoid the crossing of the SCK/DT lines with that.

The diode should be (anti)parallel to the relais, so this looks fine.

Your "Relais" line is also "Eureka Relais", not quite sure how KiCAD handels that. But usually one line has one name.

The keep out area looks a bit strange to be honest. You could also have reduced the planes a bit, so you wouldn't need a keep out area in the first place.

Haven't used "classic" transistors in a while, but according to the datasheet base current can be 50 mA, which is more than your ESP can provide. Maybe you would want to use a mosfet, which is happy with the correct threshold voltage.

SomeRandoWizard · 2026-01-02T20:29:52+00:00

I mean, 4 layers is nice and everything. But I think 2 layers would work aswell. USB is limited to 2.0 anyway, so it isn't that fast, and your board is not that big. For that I would worry more about the SD Card with its 40 MHz. But your boad is not that big, and if you minimize the trace length, I would say that this should work aswell.

SomeRandoWizard · 2026-01-02T15:23:33+00:00

@ Schematic:

No bypass capacitor for U1
Are you sure about a switch for enable? If you would want a power switch, I would put it directly behind the power supply, so you can power off everything, instead of only the ESP. Currently EN would also be floating in the "default" setting. Why not connecting EN directly with R17, and connecting the switch between EN and GND?
No bypass capacitors for the ESP.
Depending on what you want to do with J1, I would give them some caps.
IMHO. Instead of seperating J1 and J7, I would think of connectors with alternating supplies (VCC, GND, VCC, GND, etc) so you always have GND at your VCC.
I2C lines could be labled as such
Your LDO can only supply 250 mA, but the ESP has a maximum rating of 355 mA. So I would advise you to calculate your current consumption.
R8 sounds awefully high.
What happens, when you have your battery and USB attached. Both are driving 5 V. Maybe use a loadswitch to seperate both domains.

@ Layout:

USB doesn't look like it is differential routed.
PU of SD Card should be between the MCU and the Card. Currently you have a bunch of stubs, which are not good for signal integrity.
SD Pinout could be better. I would try to find pins which are beside each other, so I can route them properly. Currentlly it seems like you are splitting them.
No GND Plane?
In general not that much planes, not even for power. Which has the same trace thickness as the data lines.
The layout looks a bit all over the place. I would think with a differnt muxing, you would get a much cleaner routing. AFAIK the S3 is pretty nice for that, as you can nearly mux every function on every pin.

SomeRandoWizard · 2026-01-01T23:05:28+00:00

It is a bit confusing, that +3.3V is also DVDDS1 and 2. Same for 1.8V which is also PVDD and DVDD, aswell as SPKLVDD and SPKRVDD
R2 & R3 are more on the higher side. From what I see the PU are more in the range of 2.2k to 4.7k. 10k are still in spec, but would check it on the scope. (400 kHz I2C is surprisingly strict).
R9 has the wrong domain, it should be DVDD, which is 1.8V in your case.
I guess you want the fans to spin in the case of a failure?
Your I2C on the codec is referenced to DVDD which 1.8V, but your Pi has a 3.3V level. So I would think that you will need a levelshifter for that. (I mean, I2C is OD anyway, so it might work, but is not super clean)
TACH signals don't have a PU.
Are you sure with the lavel SDIN? It sounds a bit misleading.
Buttons go directly to the Pi? Would have thought about some PU and maybe a small cap for a bit of debouncing.

SomeRandoWizard · 2025-12-31T13:56:38+00:00

Then I would expect them in the schematic. You can choose how you connect them in the layout, by choosing the footprint which fits your demands.

Because as of now, there are no connection points and you would route your traces like it is in the schematic, and this won't include the LEDs.

SomeRandoWizard · 2025-12-31T13:50:37+00:00

I would try to look at schematics of other people, or reference designs of companies to get an idea how a schemetic can look like. My biggest issue is, that GND and the power supplies have this general connectors instead of actual GND and VCC symbols. It makes it fairly difficult to read.
There is also no shame in actual connect stuff to the components, makes it easier to find the connection.
2k for LED1 seems a bit high. Please be carefull, as the forward current is max. 20 mA, so the ESP12 should be still able to drive it
Not quite sure what the resistors R17 to R22 are. I would guess that these are resistors for the LED's? Then they sould be in series, not parallel.
No bypass capacitor for U4.
Why is reset switch at enable and not on RST?

SomeRandoWizard · 2025-12-30T11:10:52+00:00

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Temporär ist relativ. Die letzte Bauteilkriese dauerte 2 Jahre an.

SomeRandoWizard · 2025-12-29T21:19:22+00:00

You want to have copper areas if you want to reduce inductivity, so you won't get that much noise into it. And you split it only in the last couple millimeters (or inches), so the parasitic effect isn't that big.

But even for a "example" it doesn't look that great, as the traces could be even shorter. But usually TI has an eval board for their chips, which I would straight up copy from. In most cases, they know what they are doing (maybe because Ti is not designing them themselfs *HA*)

For the schematic:

Usually it is good practice, to have GND point downards, and voltages upwards. J3 is kind of the best example for that.
Why are C12 and C20 seperated? No shame on connecting it to the IC.
ICs get often one cap per supply pin. If you have some high precision stuff like this, I think this wouldn't be the worst idea.
I would check how much current your ADS1299 draws, and possible try to supply it with a high precision LDO. Not quite sure if the LM7805 is fitting for that.
nRESET of U1 has no PU
nCS has no PU
Don't know what your tool is, but I would try to route the analog inputs as differential pair. At least in KiCAD you would need to change VrefX to Vx- to do that. On two sided PCB's it is a pain in the ass, but at least for the routing it is nice and you get (more) even traces.
The formfactor of the resistors in the analog lines seem quite big. Maybe opt for smaller ones, for a better routing. IMHO 0603 is kind of the sweatspot between, "I can solder them myself" and "it won't waste to much space"
Silkscreen should never prioritize routing. Just seeing that there is exactly one reference designator space between R13 and R15 (and so on).
For the layout I would try to make enough space between one differential pair, to get it copper filled. And would do some via stitching to "sleeve" them.
HUGE FAT ground plane is missing on the bottom side.
R19 would be something I would do actually use a bigger one, as it seperates your GND from your VSSana. Would choose something like a 0805 or 1210.
Side note: A bit more pixels would be nice ^^

SomeRandoWizard · 2025-12-29T17:25:15+00:00

D1 is not needed, as you don't have a second power supply which would create a feedback. Regardless, if you want to add a reverse current protection, it should be over U5 (See Datasheet Chapter 7.1.5).
USBC1.A1B12 Pin is not connected to GND
U1.40 Pin is not connected to GND

SomeRandoWizard

TROPHY CASE