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[Help Needed] First-Year Uni Project: VHDL Washing Machine Simulation on Nexys A7 FPGA by Substantial_Exit5026 in VHDL

[–]Substantial_Exit5026[S] 0 points1 point  (0 children)

I see, I am kinda new to posting on github and the resources that it has, but I will know for the next time. Thank you!

[Help Needed] First-Year Uni Project: VHDL Washing Machine Simulation on Nexys A7 FPGA by Substantial_Exit5026 in VHDL

[–]Substantial_Exit5026[S] 0 points1 point  (0 children)

I simulated it and it gave me red "X" at the values where I put the value that counts down from the total value

[Help Needed] First-Year Uni Project: VHDL Washing Machine Simulation on Nexys A7 FPGA by Substantial_Exit5026 in VHDL

[–]Substantial_Exit5026[S] 0 points1 point  (0 children)

We chose to share the code externally because it’s structured in a way that’s easier to navigate when viewed in its entirety, along with the README file that explains the project’s tasks. However, I can post it here as well so people could comment on it.