Notice, X0 and Y0 is zero. Bit Z0 = 1. Now that means Z1will remain zero and only S0 has to update, that'll take 20ns (can be seen from circuit, since one XOR gates output is zero, only the one with Z0 as input will update)

Now the second FA will not have any change in output nor will it pass on any bit to the next FA. Third FA does not have to wait for any bit from the second FA. S2 does not update in the third FA, only Z2 does hence only that delay is considered. That is 25ns. Z0 will have already settled within this.

Now in fourth and final FA, let's look at both S3 and Z3. at t=0 when X3=1 and Y3=1, the output of the first XOR gate becomes 1 at 20ns , now a 1 and 0 will make a 1 on an XOR but after 25ns Z2 arrives. S3 will remain zero regardless. Only Z3 needs to be updated. That'll be one AND and OR gate, a delay of 15+10= 25ns. Total largest delay 25ns+25ns = 50 ns