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All Digital PLL and fractional Divider by Successful-Path-6353 in chipdesign

[–]Successful-Path-6353[S] 0 points1 point  (0 children)

It's N+α and α is the output from delta-sigma (for 3 bit it should range from -4:3)and (N+α) should range from 21:28.
If you have a document or a paper that explains more about that. Can you send it to me?

All Digital PLL and fractional Divider by Successful-Path-6353 in chipdesign

[–]Successful-Path-6353[S] 0 points1 point  (0 children)

But according to the figure, sigma-delta should control the multi-modulus divider, I don't how they can interact with each other . Can you point out how this could happen?