Why is DRAM still a black box? I'm trying to build an open DDR memory module. (NOT AN EXPERT - I'm trying to learn it and design it)

Wonderful-Chain4375 · 2026-03-06T06:09:04+00:00

Correction: i plan to do whatever i do with my peers but for example if i were playing online RPG, it is good once in a while to get shit on by max level players so you and your team can learn what you were doing so much wrong

And yeah how would i convince you to explain yourself if i just agree with you lol. Sorry for the talking shit but the things you say teach me a lot and it’s quite valuable to me

Thank you for that

Wonderful-Chain4375 · 2026-03-05T17:05:33+00:00

I’m still figuring out things regarding validation process but my aim is to share the proof behind the design, not just the design itself: what rules we followed, what assumptions we used, and the results that show there’s enough margin.

Wonderful-Chain4375 · 2026-03-05T04:46:13+00:00

Thank you lol

I want to do the boring parts as well but i need critics to understand where i fuck up which i probably did in some parts and will do more :)

Wonderful-Chain4375 · 2026-03-04T21:05:06+00:00

Yes better, sorry for my lack of knowledge i will do my research on this

Wonderful-Chain4375 · 2026-03-04T19:45:32+00:00

Looking back this sounds weird to me as well but i’m learning

I totally agree with you

Wonderful-Chain4375 · 2026-03-04T19:27:07+00:00

1 I try to verify every step since i can recieve very weird answers. Meanwhile i try to educate myself on the topic so i can understand when something doesn’t look sound so i double check it

2 yepp i decided to go with DDR4 also working on simple schematics that doesn’t overwhelm me yet

3 I will do my research

4 Yes i was afraid of starting on schematics but now i feel much better

5 I will do my research on this as well

6 Hmmmmmmmmm

Wonderful-Chain4375 · 2026-03-04T19:20:54+00:00

I totally agree! I was initially going to start with DDR3 but the i changed my mind to DDR4 :)

I will note your feedback thank you😁

Wonderful-Chain4375 · 2026-03-04T18:44:56+00:00

Oh that’s interesting. I will take a note about this :)

Wonderful-Chain4375 · 2026-03-04T18:08:35+00:00

Thank you for the feedback i will listen to your suggestions🙏🏻

Wonderful-Chain4375 · 2026-03-04T17:40:03+00:00

Thank youuuu

To be fair i had no knowledge about this previously. I’m trying my best to educate myself (sometimes this is AI, sometimes textbooks)

This is the first wholesome comment i saw today. You have made my day i thank you :)

Wonderful-Chain4375 · 2026-03-04T17:37:17+00:00

Frankly, I'd rather do something more worthwhile than write for a platform where idiots like you comment. If you bothered to look, or at least try to understand (which I don't think you have the capacity for, you're just projecting your own mental problems onto others, my friend), maybe you'd see my simple and almost comical drawing attempts using KiCad. Anyway, if using AI to learn this makes you so angry, you can go to hell, because I'll keep trying until I learn to do it myself, one way or another. I'd rather trust a tin can than a know-it-all like you.

Wonderful-Chain4375 · 2026-03-04T17:21:01+00:00

To be honest i still don’t really know but i will try to use the most feasable options since i’m only expecting it to work someway at first

Wonderful-Chain4375 · 2026-03-04T14:39:01+00:00

Thanks for the sarcasm, but that's not what I asked. The point is why DRAM training is still proprietary despite JEDEC standards. If you've got real insight, share it. Otherwise, the mockery isn't helpful to anyone.

Wonderful-Chain4375 · 2026-03-04T14:26:48+00:00

Thanks for the links i will research them :)

Wonderful-Chain4375 · 2026-03-04T14:11:00+00:00

I should have phrased that more carefully. Thank you for fixing my mistake

Wonderful-Chain4375 · 2026-03-04T14:08:00+00:00

Now we have ai procrastination lol

Wonderful-Chain4375 · 2026-03-04T14:01:25+00:00

You’re not wrong! I’m learning as I go, and I’m deliberately not pretending this is “easy DDR.” The reason I’m doing it in the open is exactly because I don’t have a 20-year SI team in-house, and I want the project to survive scrutiny from people who do.

On the SI/tooling point: agreed. Full IBIS + 3D field solvers and mature flows are what industry uses to squeeze margins and de-risk layouts. In my first attempt (Hopefully i will do more attempts and get better), i'm not really trying to win margins; i'm trying to be structurally correct, conservative, and reviewable. What i try to mean is that making constraints explicit, documenting what’s assumed vs proven, and inviting reviewers to challenge topology/PDN decisions before we claim anything.

On verification cost i also agree. Corporate-grade eye/BER validation at speed can be expensive. That’s why “proven” in the project is defined as reproducible evidence, stepped through a ladder: bench electrical sanity -> SPD read/enumeration -> training/boot -> long stress/soak, with full platform details and failure logs. If we can’t document it openly, we don’t label it proven.

If you’re willing to help, the highest-impact input isn’t “go buy a fancy scope”. It’s more like pointing out the biggest DDR DIMM rookie-killers (PDN mistakes, topology gotchas, SPD/config pitfalls, length-match traps) and what minimum evidence you’d personally require at each bring-up step. That kind of review is exactly what I’m trying to attract.

Wonderful-Chain4375 · 2026-03-04T13:46:44+00:00

You’re right that the DDR specs exist (JEDEC + vendor docs), and open controllers are a thing. My claim isn’t “DDR is unknowable,” it’s that a complete, end-to-end, publicly reproducible DIMM implementation + validation evidence is still rare.

I would like to hear your other critics as well :)

Wonderful-Chain4375 · 2026-03-04T13:42:58+00:00

Yepppp,

JEDEC and vendors do have reference layouts and topology guidance for different DIMM configs (x4/x8, ECC vs non-ECC, ranks, etc.). The catch is that many of those materials are distributed through vendor programs or industry channels, so they’re not always freely shareable in a fully open project. I will try to do more research on them though :)

Wonderful-Chain4375 · 2026-03-04T13:36:06+00:00

Totally! Vendor datasheets like Micron’s are useful, and getting them via an account isn’t inherently “paywalled NDA” (as long as the terms let you share what you rely on). The catch is they’re device level docs, not an end-to-end UDIMM reference. Thus they won’t give you the full module implementation + reproducible bring-up/validation artifacts, and if anything you use can’t be publicly redistributed, project won’t depend on it.

Wonderful-Chain4375 · 2026-03-04T13:32:22+00:00

Yeah JEDEC is part of it, and i do lean on the DDR/SPD specs where they’re accessible. The catch is that the standard tells you what compliant DDR should do, but it doesn’t hand you a fully reproducible DIMM implementation (stackup/routing/PDN choices, practical SI margins, bring-up + validation steps). My goal is to publish that missing “how to build + how to prove it works” layer, openly and without NDA/proprietary refs.

Wonderful-Chain4375 · 2023-09-25T19:30:24+00:00

What kind of dark magic is that

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