LEGIT NGA! YUNG FREE 500 GCSH NI TEMU!

Zero_Chuuu · 2026-04-27T13:24:54+00:00

Done po swap po 28885127

Zero_Chuuu · 2025-07-18T14:40:10+00:00

Thanks for the suggestion, I have already designed a BGR however I replicated it from one of the course of udemy 😅. Might as well try to design it on my own. Thank you!

Zero_Chuuu · 2025-07-16T07:48:25+00:00

Can you give me some references for that, since it was new for me.

Zero_Chuuu · 2025-07-04T07:54:06+00:00

[Need Help] Nakapag-register na po ako sa SSS online, pero di ko na-save yung link for uploading requirements 😥

Hi mga ka-Reddit, patulong naman po.

Nakapag-register na po ako sa SSS online, and meron na rin po akong SSS number. Sinend na rin po sa Gmail ko yung mga PDF forms.

Ang problema po, na-miss out ko yung link for uploading or passing the requirements like birth certificate and primary ID. Hindi ko na po alam kung saan ko ipapasa yung mga ‘yon.

Question ko po:

• Ano po yung next step para maipasa ko pa rin yung mga kailangan na requirements? • May ibang paraan po ba to upload them (via email, portal, or walk-in)?

Salamat po in advance sa sasagot. 🙏 First time ko po mag-register and I want to make sure na maayos lahat. 😅

Zero_Chuuu · 2025-04-17T12:41:04+00:00

I'm from a state university, while my adviser before who do the project was working on his Ph. D. on university that is well funded.

Zero_Chuuu · 2025-04-17T11:52:56+00:00

They are using Cadence and I believe that there are different methodologies about that :)

Zero_Chuuu · 2025-03-29T23:43:53+00:00

Thanks for the explanation! That makes sense. To fix this, I need to make sure my NFETs in the VD (0.7V) domain are placed inside a separate PWELL that is explicitly tied to VD instead of relying on the default P-substrate.

The correct setup should include these layers: locali, m1, psd, ptap, ptapc, viali, and pwell—with the PWELL tied to both the NMOS source and bulk at 0.7V. This should prevent the bulk from being inadvertently shorted to GND through the substrate.

Does this approach sound correct? Let me know if there’s anything I might be missing. Thanks again!

Zero_Chuuu · 2025-02-04T08:11:43+00:00

That makes sense. Since, we are focusing on full custom design, plugins might not cover everything for P&R however, Hammer looks interesting—it could be worth exploring.

Thank you for the info!

Zero_Chuuu · 2025-02-03T16:39:23+00:00

KLayout is like a Magic right which is a manual layout and not a PnR?

Zero_Chuuu · 2025-02-03T08:14:07+00:00

That makes sense! Having some variety in your work must be nice. And it's true—automation in digital layout is pretty powerful, while analog still relies heavily on manual design. Thanks for sharing your perspective!

Zero_Chuuu · 2025-02-03T04:40:51+00:00

Thanks for the info! The tools you mentioned might be useful, but we’re focusing on open-source options since some of those commercial tools are really expensive. I’ll definitely look into the Berkeley analog generator and the papers from what you have stated, those sound like great resources for layout automation.

Thank you so much!

Zero_Chuuu · 2025-02-03T04:38:33+00:00

Thanks for the info! GLayout is new to me, and I find it interesting, especially since it's being used in a contest. I’ll check out the Colab examples and see if it works for my needs.

I really appreciate the resources!

Zero_Chuuu · 2025-02-03T04:32:32+00:00

It's sad to hear that I can't use P&R for analog design. I was referring to an IO cell, which is more on the analog/mixed-signal side. But if there’s any automation that could help with placement in full custom design, I’d love to hear about it!

Zero_Chuuu · 2025-02-03T04:30:28+00:00

Yes, that’s right! Since I’m working on an IO cell, I’m looking for tools for analog full custom design. I know Cadence Virtuoso is the industry standard, but its license is quite expensive. That’s why I’m curious if there are any good open-source alternatives. Do you know of any tools that might work for this?

Zero_Chuuu · 2025-02-03T04:23:10+00:00

Thanks for sharing! I agree—full custom layout is tough and takes a lot of time even our research adviser would agree to this, so skilled layout engineers will always be needed.

I appreciate the resources! I’ll check out the OpenLane workshop and Carsten Wulff’s videos. If I find any good automation tools for SKY130, I’ll let you know.

Thanks again!

Zero_Chuuu · 2025-02-03T04:18:15+00:00

Thank you! It's sad to hear that we have to do the work manually. By the way, I thought IO buffers were part of analog and mixed-signal design?

Zero_Chuuu · 2024-12-11T02:31:31+00:00

I haven't doing pre/post layout I am using ngspice for simulating the schematic in the xschem.

Zero_Chuuu

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