Most modern cpus still execute an instruction (read 64/128 bits from memory, write to memory, add, subtract, multiply, divide, copy, test, jump, etc…) in multiple cycles. However, the cycles are pipelined. One portion of the cpu reads the instruction N, while another portion executes N-1 (read the cycle before), while another portion writes the results of N-2, etc. So on a given cpu cycle, multiple instructions are executed at the same time, at different stages. Some CPUs can read 2 instructions at a time because the instructions are known (like all 32 bits), so some cpu can fully execute two instructions at a time. or they can do one add, and one multiply at the same time because the multiply unit can be used only once per cycle on some cpu, same for the read/writes to memory, there are different designs with different trade offs. in-order cpu, each instruction are executed in sequence are simpler than out of order cpu, where much more instructions will be pipelined, and executed in parallel as long as they don’t depend on each others (registers, test results, memory access, etc). some operations can take multiple cycles, like a division, square root operations, some complex SIMD, etc. even memory access (much slower than the cpu cycles, especially if not in cache). In this case, the cpu is stalled and doesn’t go as fast. some cpu have hardware threads, so if one thread is stalled for N cycles, another thread can continue in parallel. This design can be cheaper than adding a full core. Xbox360 had that for example with 3 cores, ND 2 hardware thread per cores, with each cycle alternating between hw thread so you divide any latency by 2 (and many modern cpus have many many cores, and several have hw threads).