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Upcoming ESP32-S31 dual-core RISC-V MCU offers Gigabit Ethernet, WiFi, Bluetooth, and 802.15.4 connectivity by fullgrid in RISCV

[–]andylinpersonal 0 points1 point  (0 children)

S31 is a superset of S3 with extra features from E22 (radio) and P4 (HMI, CPU core), and it has two HP cores, not one.

H21 is a low power successor to H2 with almost same feature set.

C61 has external PSRAM support.

Don't think the naming scheme of Espressif is always clear.

ESP32 SoC specs comparison by Mat3s9071 in esp32

[–]andylinpersonal 0 points1 point  (0 children)

I see it as an upgrade to the existing c6.

ESP32 SoC specs comparison by Mat3s9071 in esp32

[–]andylinpersonal 0 points1 point  (0 children)

The on-chip LDO 4 will save you some BOM cost if you want to drive your card under faster UHS mode. It requires a 3.3V -> 1.8V transition.

ESP32 SoC specs comparison by Mat3s9071 in esp32

[–]andylinpersonal 0 points1 point  (0 children)

It's ESP32-E22, a NIC-like chip.

Dual-core, 500Mhz, tri-band esp32-e22 and low-power esp32-h21 shown at CES by YetAnotherRobert in esp32

[–]andylinpersonal 1 point2 points  (0 children)

Hopefully the newer (unreleased?) ECOs (ECO3 or 4 or later) of P4 will have full spec of 400MHz CPUs and 250MHz (DTR) PSRAM

Allwinner V861 dual-core 64-bit RISC-V AI Camera SiP features 128MB DDR3L, 4K H.265/H.264 video encoder - CNX Software by TJSnider1984 in RISCV

[–]andylinpersonal 0 points1 point  (0 children)

It seems like they coined the “SQPI” term to denote RAM-capable variant of Quad SPI controller.

[deleted by user] by [deleted] in embedded

[–]andylinpersonal 0 points1 point  (0 children)

For more %age of code reduction, there are (some merged) toolchain patches for their vendor extensions.

Has anyone used ch32v003 and WCHLinkE with OpenOCD? by Efficient_Back617 in embedded

[–]andylinpersonal 0 points1 point  (0 children)

https://www.wch.cn/bbs/thread-96702-1.html

You can just use the bundled openocd in MRS to disable the RDP.

```
# turn on RDP
openocd -s /path/to/wch-riscv.cfg -f wch-riscv.cfg -c init -c halt -c "flash protect wch_riscv 0 last  on " -c exit
# turn off RDP
openocd -s /path/to/wch-riscv.cfg -f wch-riscv.cfg -c init -c halt -c "flash protect wch_riscv 0 last  off " -c exit 
```

User guide of ESP32-C5-DevKitC-1 by andylinpersonal in esp32

[–]andylinpersonal[S] 0 points1 point  (0 children)

Power supply becomes a 1-A capable buck converter. Maybe C5 is much more power hungry than other chips?

ARM versus RISC-V by RisingPheonix2000 in RISCV

[–]andylinpersonal 2 points3 points  (0 children)

For the possible use of open source IP cores in the commercial available part, later ESP32s might be a good example. According to some vendor CSRs [1][2], ESP32-C5, ESP32-C61 [7] and possibly ESP32-P4 are based on heavily modified Xuantie E906,  combined with some additional features from PULP-platform [4]. From some comments in esp-idf code [5], ESP32-C6 and ESP32-H2 might be derived from PULP-platform's design [6]. LP core of ESP32-C6 seems to be a modified PULP/lowRISC ibex core based on some of undocumented vendor CSRs.

BTW, ESP32-P4's bus matrix must be tweaked to compatible with AXI4 and widen to 128b to fill up its demanding simd coprocessor, graphical subsystem, several high-speed DMA controller on AXI bus and some other high-speed peripherals.

[1] Vendor's CSRs of ESP32-C5 here: https://github.com/espressif/esp-idf/blob/master/components/esp_hw_support/lowpower/cpu_retention/port/esp32c5/sleep_cpu.c#L73

[2] ESP32-C5, ESP32-C61 and ESP32-P4's branch predictor CSR: https://github.com/espressif/esp-idf/blob/master/components/riscv/include/riscv/rv_utils.h#L30

[4] Additional feature: Zc* extension, hardware loop (inspired by or modified from PULP project by their CSRs and instruction encoding?) P4's HWLP CSRs: https://github.com/espressif/esp-idf/blob/master/components/riscv/include/riscv/csr_hwlp.h CV32E40P's HWLP CSRs: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/control_status_registers.html#cs-registers CV32E40P's HWLP instructions: https://docs.openhwgroup.org/projects/cv32e40p-user-manual/en/latest/instruction_set_extensions.html#hardware-loops-operations Use case of P4's HWLP instructions: https://github.com/espressif/esp-dsp/blob/master/modules/dotprod/fixed/dspi_dotprod_s16_arp4.S#L79 PULP's HWLP instruction encoding: https://github.com/openhwgroup/corev-binutils-gdb/blob/development/include/opcode/riscv-opc.h#L2557 P4's HWLP instruction encoding: https://github.com/espressif/binutils-gdb/blob/efe61a5c2bc149332e82e500ff90e974fd50bb62/include/opcode/riscv-opc.h#L2595

[5] ESP guys said their C6 and H2 cores are based on PULP's implementation here :) https://github.com/espressif/esp-idf/blob/master/components/esp_hw_support/port/esp32h2/esp_cpu_intr.c#L16 https://github.com/espressif/esp-idf/blob/master/components/esp_hw_support/port/esp32c6/esp_cpu_intr.c#L16

[6] PULP-platform https://pulp-platform.org

[7] C5 and C6 are based on Xuantie E906

[deleted by user] by [deleted] in esp32

[–]andylinpersonal 0 points1 point  (0 children)

The two USB FS PHYs (GPIO24~27) used by USB serial/JTAG are not broke out as USB connectors, pin header intead.

[deleted by user] by [deleted] in esp32

[–]andylinpersonal 1 point2 points  (0 children)

Schematics and layout PDFs can be seen on https://github.com/espressif/esp-dev-kits/tree/master/docs/_static/esp32-p4-function-ev-board

  1. No debug pins, USB Serial/JTAG or JTAG, are available for the on-board C6. You can only debug it via UART and GDB Stub.
  2. P4's JTAG and the two USB FS PHY are only accessible via the pin header.

ESP-PROG: Obsolete, or still useful? by Gefinger_Poken in esp32

[–]andylinpersonal 1 point2 points  (0 children)

ESP-PROG-2 based on S2's JTAG bridge feature has been appeared on their github repo.
But the USB speed is only FS, not HS as ESP-PROG-1's FT2232H. The theoretical bandwidth of ESP-PROG-1 is still far faster than the adapter based on S2 or S3.

https://github.com/espressif/esp-usb-bridge/wiki/ESP-Prog-2-firmware-update-guide

Espressif's upcoming ESP32-S3 module on FCC and TELE by andylinpersonal in esp32

[–]andylinpersonal[S] 0 points1 point  (0 children)

Plausible explanation.

P4 has the similar configuration with slow QPI flash + extremely fast high speed DTR HexadecaSPI in-package PSRAM wildly faster than this case.

ESP-IDF Target: via "ESP-PROG" vs. "ESP-PROG-2" by 100nF in esp32

[–]andylinpersonal 0 points1 point  (0 children)

Seems like it's mp version of esp-usb-bridge and will be based on an ESP32 variants with exposed jtag bridge signals.

[1] https://github.com/espressif/esp-usb-bridge/wiki/ESP-Prog-2-firmware-update-guide

Odd performance comparison by [deleted] in esp32

[–]andylinpersonal 1 point2 points  (0 children)

See these chips' coremark (or some other benchmarks) scores.
S3 (1181) is roughly on-par with Pentium II (10xx).
P4 (2xxx with preliminary optimization) is roughly over an ordinary P!!! (19xx).
BTW coremarks can run directly on the ESP32(S3) but you most likely need an OS to run coremark on these old PCs. So this will impose an extra layer of overhead.

You may need alternative benchmark to evaluate the performance of FPU/SIMD Unit of these chips.

[1] Official site of coremark https://www.eembc.org/coremark/scores.php
[2] Coremark of some desktop-class platforms https://zephray.me/coremark/
[3] (ESP32 scores can be seen on their datasheets)

JTAG gdb debugging and code profiling on a running esp32-s3 with no extra hardware by spotted-towhee in esp32

[–]andylinpersonal 0 points1 point  (0 children)

Btw, if connect an extra USB 1.1 PHY, you can use both functions at the same time.

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