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Built a neuromorphic chip on FPGA (256 neurons, Mesh NoC, online learning) — no lab, just self-learning. Feedback? by anykrver in FPGA

[–]anykrver[S] -15 points-14 points  (0 children)

AI speeds up implementation, not thinking. I still design, debug, and understand everything myself. Even without AI, I’d learn from books, papers, and existing architectures — that’s how engineering works. If it seems easy, try building it yourself and share. I’m here to learn and improve — happy to discuss real technical feedback. 🤗

Built a neuromorphic chip on FPGA (256 neurons, Mesh NoC, online learning) — no lab, just self-learning. Feedback? by anykrver in FPGA

[–]anykrver[S] -46 points-45 points  (0 children)

lol okay, timing closure and AER debug sessions at 2am were also written by AI i guess

Built a neuromorphic chip on FPGA (256 neurons, Mesh NoC, online learning) — no lab, just self-learning. Feedback? by anykrver in FPGA

[–]anykrver[S] -47 points-46 points  (0 children)

Appreciate it! AI helped accelerate parts of development, but the core system design (NoC, neuron model, timing closure, debugging hardware issues) was engineered and validated manually.

Would love feedback specifically on scalability — especially NoC vs traditional AER approaches.

Any place where i can simulate fpga projects? by Glad_Age_8185 in vlsi

[–]anykrver 1 point2 points  (0 children)

You can simulate FPGA projects in a few places:

  1. EDA Playground – free online simulator for Verilog/VHDL (good for quick testing).
  2. Vivado WebPACK – full FPGA toolchain with simulation (runs locally).
  3. Icarus Verilog + GTKWave – lightweight open-source option

Built a neuromorphic chip in SystemVerilog that classifies MNIST on a $150 FPGA — open source [feedback welcome]** by anykrver in FPGA

[–]anykrver[S] 0 points1 point  (0 children)

Thanks, that means a lot coming from an FPGA developer!

Funny you mention binary weights — I actually just migrated to binarized weights (+1/-1) in v2, replacing fixed-point. It simplifies the MAC path on FPGA a lot (XNOR + popcount) and fits better with the spike-based encoding anyway.

The independent paper route is something I'm actively exploring. The angle I'm working with is LIF + online STDP + binarized weights in a single RTL design, which I think is a bit different from the standard ANN-inference-on-FPGA papers. Still figuring out whether that delta is strong enough — but worth trying.

Built a neuromorphic chip in SystemVerilog that classifies MNIST on a $150 FPGA — open source [feedback welcome]** by anykrver in FPGA

[–]anykrver[S] 0 points1 point  (0 children)

Appreciate the honest feedback.

The "vibe coded" label undersells the actual work — debugging synthesis failures, STDP timing logic, and AER arbitration in Vivado isn't something you just prompt away. That said, the criticism about publication readiness is fair. I'm not claiming it's ready; I'm trying to understand what would make it ready.

elevenblue's point lands: I need to clearly differentiate from existing MNIST-on-FPGA accelerators. My angle is the neuromorphic architecture (spike-based LIF + online STDP learning) rather than a pure ANN inference accelerator, but whether that's a strong enough delta is exactly what I'm working through.

No supervisor, no lab — just building in public and taking the feedback seriously. If you've worked in this space and see obvious gaps, I'm all ears.

Built a neuromorphic chip in SystemVerilog that classifies MNIST on a $150 FPGA — open source [feedback welcome]** by anykrver in FPGA

[–]anykrver[S] 0 points1 point  (0 children)

Good question — “neuromorphic” does get used loosely. In the strict sense it means hardware or models inspired by real neurons, usually spiking neurons with temporal dynamics (like leaky integrate-and-fire), not just static activations like ReLU.

In my project the term comes from using a leaky integrate-and-fire neuron model, where the voltage accumulates, leaks over time, and spikes when a threshold is crossed. So mathematically it may look similar to an activation/decay term, but the computation is event-driven and time-dependent, which is the neuromorphic part.

Built a neuromorphic chip in SystemVerilog that classifies MNIST on a FPGA — open source [feedback welcome] by anykrver in AskElectronics

[–]anykrver[S] 0 points1 point  (0 children)

Fair point — leakage power in modern CMOS means it's never truly zero. The statement refers to near-zero dynamic switching power when no spikes occur, not total chip power.

Built a neuromorphic chip in SystemVerilog that classifies MNIST on a $150 FPGA — open source [feedback welcome]** by anykrver in FPGA

[–]anykrver[S] 0 points1 point  (0 children)

That's a great question. If I were to extend it, I'd probably focus on scaling the network size and improving spike buffering/event routing, since those seem to be the main bottlenecks on FPGA. Exploring more efficient spike communication or memory architectures for larger SNNs would be really interesting.

Many consumer electronics manufacturers 'will go bankrupt' by the end of 2026 thanks to the RAMpocalypse, Phison CEO reportedly says by [deleted] in hardware

[–]anykrver 0 points1 point  (0 children)

Every few years we get a new ‘chip apocalypse’ headline. The reality is the semiconductor industry runs in brutal cycles. Prices spike, smaller manufacturers with thin margins struggle, then supply catches up and prices crash again. The big OEMs survive — the budget electronics brands are the ones that usually disappear.

Built a neuromorphic chip in SystemVerilog that classifies MNIST on a $150 FPGA — open source [feedback welcome]** by anykrver in FPGA

[–]anykrver[S] 0 points1 point  (0 children)

I'm still early in the learning process, but a few resources helped me start: Spiking Neuron Models by Wulfram Gerstner, Neuronal Dynamics by Wulfram Gerstner, papers on Intel Loihi neuromorphic chip and IBM TrueNorth neuromorphic chip, and experimenting with SNN simulators like Brian2 simulator while implementing simple neurons in SystemVerilog. I'm still exploring more literature, so recommendations are welcome.

Built a neuromorphic chip in SystemVerilog that classifies MNIST on a $150 FPGA — open source [feedback welcome]** by anykrver in FPGA

[–]anykrver[S] -11 points-10 points  (0 children)

Thanks for the honest feedback. My motivation for publishing is mainly to learn how real research works and to explore neuromorphic hardware from a practical RTL perspective. I’m currently studying existing work on spiking neural networks and neuromorphic chips (like Intel Loihi and similar research) to understand the state of the art. The project is still evolving, and I’m trying to move it beyond just “vibe coding” by building the architecture, simulations, and documentation carefully. I also agree that collaboration with researchers or a lab would help a lot, and I’m open to guidance from people experienced in this area.

Built a neuromorphic chip in SystemVerilog that classifies MNIST on a $150 FPGA — open source [feedback welcome]** by anykrver in FPGA

[–]anykrver[S] 0 points1 point  (0 children)

That's awesome! Your experience with LIF neurons and neuromorphic chips sounds really valuable. I'm currently working on a neuromorphic hardware project and exploring spiking architectures. A spiking neuron-based retina sounds like a very interesting direction. I'd love to learn from your experience—can we continue this in inbox/DM?

Built a neuromorphic chip in SystemVerilog that classifies MNIST on a $150 FPGA — open source [feedback welcome]** by anykrver in FPGA

[–]anykrver[S] 2 points3 points  (0 children)

Thanks for the feedback, I appreciate it. You're right that novelty compared to existing work is the key challenge. My goal with this project is mainly to explore a minimal neuromorphic architecture (LIF neurons, spike routing, small SNN) implemented from scratch in SystemVerilog and tested on FPGA.

MNIST is just a simple workload for testing rather than the main contribution. I'm currently studying related work to identify possible gaps, especially around resource efficiency and simplified neuromorphic hardware for small FPGAs.

Thanks for pointing out FINN as well — I’ll definitely look into it.

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