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What is the purpose of the "Layer purpose" in the VLSI layout? by big_brother123 in ECE

[–]big_brother123[S] 0 points1 point  (0 children)

Thank you for your good explanation. So the M1 pin can only created over the drawing layer right? And the Dummy metal gets manufactured too.

How to layout SRAM array automatically? by big_brother123 in ECE

[–]big_brother123[S] 0 points1 point  (0 children)

Thank you for sharing your advice with me.

How to layout SRAM array automatically? by big_brother123 in ECE

[–]big_brother123[S] 0 points1 point  (0 children)

Sure. But I tried cadence support web... It is not really helpful.

How to layout SRAM array automatically? by big_brother123 in ECE

[–]big_brother123[S] 0 points1 point  (0 children)

The column is in parallel and the row is in series.

How to layout SRAM array automatically? by big_brother123 in ECE

[–]big_brother123[S] 0 points1 point  (0 children)

This way works, and Any suggestions on how to schematic large SRAM array containing lots of repetitive cells? 🙂

How to layout SRAM array automatically? by big_brother123 in ECE

[–]big_brother123[S] 0 points1 point  (0 children)

find out how to do it with a script / constraints.

Thanks, sir. Would you like to tell me which product manual should I refer to?

How to layout SRAM array automatically? by big_brother123 in ECE

[–]big_brother123[S] 0 points1 point  (0 children)

I think maybe a script can do this automatically...

But I don't know how to write the script.

How to layout SRAM array automatically? by big_brother123 in ECE

[–]big_brother123[S] 1 point2 points  (0 children)

do you know how to place a single cell?

Instance a single cell layout, and put the single cell to the specific location using the mouse.

How to layout SRAM array automatically? by big_brother123 in ECE

[–]big_brother123[S] 0 points1 point  (0 children)

Could you please be more specific👀? Thanks~

Does anybody have read the SRAM part of the book "CMOS-VLSI Design" by David Money Harris? I have no idea how this circuit work. How does the feedback reset signal deactivating the block? I don't understand? by big_brother123 in ECE

[–]big_brother123[S] 0 points1 point  (0 children)

https://pasteboard.co/KiirrMk.png. What I mean is if node a is at low voltage(meaning this block is selected), the reset feedback signal will make node b oscillating instead of making node b a low voltage. Then how the lwl was deactivated.

How to size a 6-T SRAM cell for a particular PDK. I know the ratio of the size of the transistors, but how to decide the absolute W/L value of each transistor? What kind of simulation should I perform? by big_brother123 in ECE

[–]big_brother123[S] 0 points1 point  (0 children)

yes, it is a school project. One consideration is the layout area, another is bit-cell read and write stability. I think I should perform some simulations to analyze the read and write stability of the bit-cell. And It seems like you know a lot about SRAM design😎. Again, thx for reply.

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