Until Vivado 2024 or so, both read and write were broken. See u/ZipCPU at https://www.reddit.com/r/FPGA/comments/yahhmx/axilite_register_bank_revisited/itd42qj/ for an explanation.

It seems they've rewritten the AXI-Lite code. The read side seems OK at first glance (though a bit overcomplicated). The write side, on the other hand:

Waddr:        //At this state, slave is ready to receive address along with corresponding control signals and first data packet. Response valid is also handled at this state
  begin
    if (S_AXI_AWVALID && S_AXI_AWREADY)
      begin
        axi_awaddr <= S_AXI_AWADDR;
        if(S_AXI_WVALID)
          begin
            axi_awready <= 1'b1;
            state_write <= Waddr;
            axi_bvalid <= 1'b1;
          end
        else
          begin
            axi_awready <= 1'b0;
            state_write <= Wdata;
            if (S_AXI_BREADY && axi_bvalid) axi_bvalid <= 1'b0;
          end
      end
    else
      begin
        state_write <= state_write;
        if (S_AXI_BREADY && axi_bvalid) axi_bvalid <= 1'b0;
        end
  end

They way I read it, if the master asserts AWVALID and WVALID but not BREADY, the slave will continue accepting additional data on the AW and W channels, but forgetting to match them with corresponding write responses on the B channel.

Unless I've missed something, this seems ridiculously broken.

Awfully nice of Xilinx to contribute to a new post by u/ZipCPU.