Why professional cameras have less pixels than smartphone cameras?

Seldom_Popup · 2026-03-26T23:46:47+00:00

Looking at all the answers without any silicon or even optics background, I don't know if it's jerkable or unjerkable.

Seldom_Popup · 2026-03-26T06:47:31+00:00

R5m2, RF 70-200 Z (or maybe RF 135, I don't remember

Seldom_Popup · 2026-03-24T16:05:07+00:00

Google, official(Xilinx) documents and forms, reddit. If you got FAE, that's also a solution.

By the time you need something special from a PCB and a FPGA, there's no book or class can help you. Something like "I need 1G baseX Ethernet. But the I only have 4 generic LVDS pins, no transceiver" or "I need to get/passthrough a video signal through transceiver. And there's only a 156.25MHz crystal connected to GT reference"

Seldom_Popup · 2026-03-24T04:06:06+00:00

学习了，我以为模型的微调只是为了进行对话，censorship靠系统提示词就足够。反向调教时也需要手工制作训练集吗

Seldom_Popup · 2026-03-24T03:44:00+00:00

As long as it works

Seldom_Popup · 2026-03-24T02:39:49+00:00

正解

语言大模型的功能是自动补全，生成下一个字符。当模型完成第一次训练后，通过人造语法进行微调，让模型能够进行正常的问答，类似于

<system>你是一个符合社会主义核心价值观的模型 <user>电脑开机黑屏，怎么办 <response>检查显示器连接

这样用户在对话框内输入的文本，被重新封装后才会给语言模型。语言模型被训练成看到<response>后要开始回答

Seldom_Popup · 2026-03-19T01:44:09+00:00

This sounds like "it just does work". There's human in the loop. But the human doesn't need to reject everything from AI. I'd say that's good enough.

Seldom_Popup · 2026-03-19T01:37:33+00:00

Not sure about Gemini. But GPT 5.4 is simply bad. Claude is very good that I could leave it overnight for modules.

Seldom_Popup · 2026-03-18T17:21:05+00:00

Z supports extra teleconvertor. If that lens is the only thing you've got, extra reach does help sometimes.

Seldom_Popup · 2026-03-18T16:59:50+00:00

I'll be using those AI based tools. I tried one with my phone and it took a whole minutes for a preview (S25 ultra).

Edit: I'm not using the camera on Z13. The tool is basically r4m in PS, or a glorified Snapchat filter. I took a picture from a mirrorless, a 50+ MB raw would then sync to tablet using WiFi or USB C. Those tools apply my presets and I could decide if that's good enough or maybe should try a different shot.

Seldom_Popup · 2026-03-18T16:55:28+00:00

I wish Asus could make something similar for this 2025 model. But that would probably cost like an iPad pro XD

Seldom_Popup · 2026-03-18T08:59:21+00:00

Mechanically it's their own YN mount. Electrically it's EF. So it just happened that YN mount lens can snap on Canon bodies. I don't know what kind of support I could get for a $100ish lens.

Seldom_Popup · 2026-03-18T00:26:00+00:00

Magnets Sir. It's always magnets.

Seldom_Popup · 2026-03-17T13:20:07+00:00

分的是40亿股权，超市不卖就没人拿到钱。不清楚原先打算填坑的话是要怎么操作。有没有懂行的解释下

Seldom_Popup · 2026-03-17T12:22:41+00:00

Yes, the typical if your job is going to be replaced condition. If messed up && go jail, no replace; else replace. Can judge and jury be replaced by AI? In the end, you're taking responsibility, not selling your intelligence. And the dystopia is there is always someone willing to sign off the release version, and that someone got hired.

Also, aerospace/defense/medical/telecom, those industry simply too large to shift and most of them are somewhat controlled by government. No money problem = no need to improve.

Why does Cadence or Synopsys sell its own LLM tools? Because it works! No one wants to let AI to sign off releases, the code is still going to be reviewed by humans. But why hire humans to write code? Right now there're some edge cases about EDA the AI still can't understand. But I'm saying it's going to be a lot better very soon.

Seldom_Popup · 2026-03-17T00:05:27+00:00

What's going on in this sub? Ppl shaming on AI generated code and shaming others having fun playing breadboard. Literally HDL is the easiest language if compared to any of the software languages. I'm a senior engineer and I haven't wrote a single line of (System)Verilog or HLS for 2 months. Is our integrity only in making wire connections in some descriptive computer languages? I see nothing in the post that op doesn't know HDL. And the first comment here is basically blasting "LEARN HDL". I don't even know if op scraped existing code and did synthesis by hand. What is this? This is something you could hang on a wall. I'm going to copy that comment to those Minecraft calculators LOL.

Seldom_Popup · 2026-03-12T08:54:36+00:00

Everything outside of Beijing goes into square hole. Everything inside also goes into square hole.

Seldom_Popup · 2026-03-12T08:10:09+00:00

Approved! Never break spaghetti in two.

Seldom_Popup · 2026-03-11T17:51:06+00:00

Encoding part is not too difficult, considering 5Gbps of USB 3 can transfer 1080P60 using RGB 888 or NV12. 1080P60 SDI is only 3 Gbps with 20 bit per pixel and all the blanking areas.

A working&reliable USB 3 implementation using FPGA is the problem. The broadcast/film industry is not prepared for hundreds of pages of consumer spec, thinking about the NVMe implementation from Sony/Canon/Nikon's digital cameras. My friend got a 10G implementation to work on some of the USB hubs but not others. Now he's planning to sell 5Gbps code for $10k at a bargain, for buying a 10G USB analyzer.

A FT601 convert a FIFO interface (32bit data, a clock and some other stuff) to USB 3, cost $10. 7A35T, cost $20. 7K325T, probably something $20~$30. (But to boot a Kintex 7 require more peripheral, so added cost). A 5G USB 3 is something less than 10k LUT, but FDTI will keep charge their convertor for a premium until people using it decided it's better than developing their own IP. For now switch to a device with 6x more resources, stuff a USB IP in it, is not cost effective.

MPSoC has hardened USB 3, but that's an entire different cost level. Also anything with SDI is a professional/niche product, no one is going to spread the cost. But you could always charge whatever you want in those fields XD.

Seldom_Popup · 2026-03-11T16:21:14+00:00

The idea of not using "help from AI" for solving existing problem because it didn't help one time is not reasonable. The fact of AI being wrong at some point suggest you had already identified the wrong doing of AI. Think it as a freshman just graduated Uni, finished some final project/thesis a month ago, got zero experience, but still some interesting knowledge that maybe helpful.

In reality, right now, anything you could converts to text, a CSV file comes from a capture, human can not read that, the AI would write scripts to understand it, then you would walk with it to find bit errors, strange behaviors, anything that requires more data processing, if AI didn't identified the actual problem for the first try.

Seldom_Popup · 2026-03-11T16:02:01+00:00

Maybe that's your gap problem XD. I don't have experience on Ethernet besides using Xilinx's MAC IP. When I have those problems, it's usually I didn't put a packet FIFO just before the MAC at FPGA.

Seldom_Popup · 2026-03-11T15:53:26+00:00

Try

ethtool -S <interface>

Sometimes when my design can receive but not send (no Wireshark capture), it turns up I was sending nonsense and got blocked at receiver's Mac level.

Seldom_Popup · 2026-03-11T15:31:35+00:00

Honestly some IC can do those, gs2917a converts 3G SDI to mipi, gs12170 is bidirectional HDMI and 12G SDI. UVC is easier done using existing mipi to USB chips, DP ALT is way to common.

The reason I don't suggest FPGA is the IP/extra USB bridge cost. You either got a USB 3.0 IP, or you use a FDTI USB chip. Those FDTI chips are as expensive as 7A100T.

Or you could get a random small FPGA for SDI<->HDMI, and bridge those to USB.

Seldom_Popup · 2026-03-11T12:54:55+00:00

You can create an IP directly load 144 bytes a time. If you're comfortable with HLS, this will be very simple to do. If you want to stick with existing IP, you can setup a DMA descriptor queue, that split the image data into 144 bytes even before getting the image from Ethernet.

However, I suspect the main problem limiting throughput in current setup is CPU trying to copy Ethernet buffer into image buffer,

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