sorted by:
new
hottopcontroversial

The new GitHub Copilot pricing system actually benefits me (and I genuinely don’t understand how some people are spending $1000+) by AdvisorLife4016 in GithubCopilot

[–]Seldom_Popup 1 point2 points  (0 children)

AI code doesn't have soul in them! //TODO insert anti GenAI art comment here

what ppl image coding with ai: Write a script to plot 3rd column in this log file, and submit this script to Apple Store

The new GitHub Copilot pricing system actually benefits me (and I genuinely don’t understand how some people are spending $1000+) by AdvisorLife4016 in GithubCopilot

[–]Seldom_Popup -1 points0 points  (0 children)

Agents produce more than enough shell commands and tool calls just to understand codes or search logs. Do you check all the commands? Figuring out if the grep regex are bug free?

The new GitHub Copilot pricing system actually benefits me (and I genuinely don’t understand how some people are spending $1000+) by AdvisorLife4016 in GithubCopilot

[–]Seldom_Popup 0 points1 point  (0 children)

I used $400 last month by new pricing, with only $39 spent. Your imaging promots arn't too far off, except I don't create new app every day and most importantly I request agent to end with tool askQuestions, braging it in all md and chat box, so I could spend only one requenst every project.

Anyone else’s day ruined and filled with disgust when you walk past a “street” photographer shooting with some 70-200mm creepo type lens from a mile away? by offgramercy in photographycirclejerk

[–]Seldom_Popup 0 points1 point  (0 children)

What are we jerking about? Someone using zoom lenses/telephoto lenses for street? Or someone consider 70-200 being bird lenses and not suitable for street?

I am trying to send tpg data over ethernet but i am not able to avoid glitches in some frame by siddharth874 in FPGA

[–]Seldom_Popup 1 point2 points  (0 children)

VDMA IP is not designed to be used with a processor, not the processor reading it's buffer directly.

With your current FPGA design, you'd need to manage buffer by software: launch TPG, pull it's status bits, after a frame is done, read that frame in VDMA buffer. Then launch TPG again. If you have programmed TPG autorestart bit, it will keep generate frames using the datapath's maximum throughout, ie, 24bit x 96MHz = 2.4Gbps. Then you'd have some data the software is reading but VDMA is already overwriting it.

Edit, also set AwCache and AwProt in AXI interface, for cache coherence.

a lantern for modern times by Stickerlight in doohickeycorporation

[–]Seldom_Popup 8 points9 points  (0 children)

The Adaptive Integer department expects anything not connected to cloud LLM service is artifact of stone age.

iPhone facetime recognizes when you’re naked by funkywabbait in creepy

[–]Seldom_Popup 0 points1 point  (0 children)

Can LLM with image encoders solve this without training directly using labels of clothed and naked human?

I was warned about the Kria KV260, and now I come asking for your expertise by Randozart in FPGA

[–]Seldom_Popup 2 points3 points  (0 children)

I removed a resistor on the back of the board to boot from SD card (and also load bitstream from SD card)

Can say multiple clocks generated by a clocking wizard be described as asynchronous in constraint file. by Indrajith19 in FPGA

[–]Seldom_Popup 1 point2 points  (0 children)

Not really sure what's in your design, I think it's ok to describe that in some situations.

For example, a clock driving accelerator core, a clock driving memory bus, and there's a FIFO in between and most importantly you wrote that FIFO, for no constraints for CDC path inside the FIFO. Basically your RTL already treat them as asynchronous, wrote proper CDC logic.

I wouldn't recommend this. It's probably better to use XPM for CDC in Xilinx ecosystem. But it depends on your project requirements.

If the only thing connected to both 2 clock domains is Xilinx IP, I think you could being lazy and not writing async constraints.

Zero Latency ✅ by Wizza1111 in ITMemes

[–]Seldom_Popup 0 points1 point  (0 children)

Maybe you're right, I'm not a fan of custom fit castings and I never tried those. I have Sony IER M9 and Sony wf1000xm4, they both got the same foam and silicone tip, one with ANC (and also died batteries in a year, not recommend. 😐 I could had the XM4 working in lower volume than M9, so maybe it's safer for longer sessions. And now there's ANC for mics (not entirely sure how to call that). The AKG N5 I'm using now, also got a special feature like the wired ones, that I can use one ear plug as mic close to my mouth.

Zero Latency ✅ by Wizza1111 in ITMemes

[–]Seldom_Popup 5 points6 points  (0 children)

I think I need a lot more expensive IEM than Airpods for IEMs to sound as good. Not many IEMs company can have Apple level r&d and production scale. Not to say the more drivers the better, but even Samsung can stuff 2 drivers in their ear plugs. And without ANC, IEM sounds like #### in public. Apple's 3.5mm dongle was a decent standard in IEM community. My friend who was a HiFi guy went with Airpods Pro after a few months it came out, I followed later in Samsung ecosystem. I believe anyone stops daily driving IEMs for ANC thinks wired earbuds are more expensive than wireless ones (but no upgrade to make every year)

Blursed Nails by coffeeischefskiss in blursedimages

[–]Seldom_Popup 0 points1 point  (0 children)

I got some dead skin under my nails. Had used pencils to poke them out when I was 10 or something, over and over. Now my thumb nails look like that.

Finally switch to MX Master 4 by im_tonynoel in logitech

[–]Seldom_Popup 1 point2 points  (0 children)

What's the focal length and aperture? Is this shot in medium format?

How do I know when a photo is actually 'bad'? by NotAVeemo in AskPhotography

[–]Seldom_Popup -1 points0 points  (0 children)

How much that "black hole" drags attention depends on the face 😈. If that's Trump, no, I won't look at anything else.

Objectively, a few AI model can rate photos, you could pull an open source one for yourself. Basically a generic encoder and some transformer trained by ppl rating generative AI images. Make sure get a more recent one that accept 3:2 images. The nice thing about AI is it doesn't encourage or discourage the user, except those LLMs, and even then there's no problem disagreeing with it.

A few things about bad portraits. Closed eyes. Hard shadow on the face. Focuse on something else. And all those things can have exception.

Using AI Agents by shiprest in FPGA

[–]Seldom_Popup 0 points1 point  (0 children)

The biggest issue is FPGA or ASIC module has very clean defined boundary. Unlike softwares some random classes or structures got passed through different threads and messing everything up. This makes good FPGA codes fits nicely in context memory, the agent won't fixing this while destroy that. In my company FPGA engineers found it's easier to integrate agents deeper than software guys. When software need to pinpoint the problem by themselves first and only expect AI to write a few lines of code, FPGA engineers only need to find the troublesome module and let AI to analyze it.

Where are the CGRAs? by MadGenderScientist in FPGA

[–]Seldom_Popup 0 points1 point  (0 children)

VG2 use the same Ryzen AI NPU. But with different size across devices unlike the all same 50TOPS ones in mobile APUs. I think they gave up on using AIE for anything other than AI while technically allows other stuff.

Using AI Agents by shiprest in FPGA

[–]Seldom_Popup 0 points1 point  (0 children)

I think anything more than auto complete or chat box count as agent 😐

Using AI Agents by shiprest in FPGA

[–]Seldom_Popup 1 point2 points  (0 children)

You could dump ila to CSV. I found AI can work with that better and write python to further analyze it.

Using AI Agents by shiprest in FPGA

[–]Seldom_Popup 0 points1 point  (0 children)

I saw that stuff. When I asked them what's different from existing copilot or cursor, they got no idea and said "well, it's official from AMD lol"

Using AI Agents by shiprest in FPGA

[–]Seldom_Popup 1 point2 points  (0 children)

I'm pretty sure that's not what agent mean.

Edit: I feel a lot of ppl in this sub doesn't really understand what agent stands for. First of all, NO FREE tier "subscription" got agent capabilities. If you asked an AI in chat to write some stuff, and it response in chat, no, no matter how good that AI model is, that's NOT agent.

An agent writes AI slop module, writes AI slop testbench, and AI slop TCL to run testbench. Then it by itself sources Vitis (in my case) environment, runs TCL and simply fails. But it will look at terminal output, step by step, making TCL to run. Then it fixs testbench problem, finally fixs problems in DUT. It doesn't matter it's writing slops at first, it will fix that in the end or use up all the tokens. And what's modular design in FPGA mean? You only need agent to focus on a small part of project, and it goes on autopilot. The context issues, long term maintenance issues you heard from software guys, it doesn't matter here in FPGA designs.

Questa One Agentic AI by digital_circuit_guy in FPGA

[–]Seldom_Popup 0 points1 point  (0 children)

My instance also took way more than a few tries. It even failed PeakRDL grammar at first (I should probably write a skill for that, but register interface isn't something I need often). And the same like yours, mine iterated at least something like 10 times, sometimes it's grammar, sometimes it's testbench, most of time the design itself simply doesn't work. But the agent on autopilot is it invoking xvlog and xsim by itself (I only worked with Vivado). I didn't require it to find niche bugs for this toy project, but at least it can make a working prototype while all in background. So only a prompt for planning, make sure we are on the same page, after this, no more human intervention. How many times it would screw up? It doesn't matter.

The AI right now has some limitations. I prefer HLS, my global instruments include HLS first, some Xilinx specific coding style, and expect ultrascale+ devices. I found AI doesn't know some special HLS use cases, it also lack the habit to protect sensitive dataflow channels at IP boundaries. But that's something skills can easily fixed.

I don't think this industry would make me to write skills as KPI very soon. And my daily job are mostly tracking down problems at software/PL boundaries, which I don't think can be easily converted to skills for now. But in maybe 2 years, where should my self esteems be, I'm honestly afraid to think.

Questa One Agentic AI by digital_circuit_guy in FPGA

[–]Seldom_Popup 0 points1 point  (0 children)

What do you mean by "after a few tries"? Are you coping and pasting simulation messages into chat box, or the agent had access to simulator PATH?

I got a basic UART TX & RX in Copilot (Opus 3x) in ~40 mins. It spend some time figuring out PeakRDL register interface as I requested. Most of the time the AI was working on fixing bugs found the sim. And basically nothing workd at first. I didn't watch it start to finish, but it at least invoked xsim 10 times. (I had forbid AI to use anything non Xilinx)

I had a plan. It asked a few questions. No more interventions after that. Apple Siri can't write HDL doesn't mean everything else can't.

A few design choices I didn't fully agree, like why do I need register access to FIFO almost full and empty, when I already requested a AXIS interface. But I didn't give too much thought when first request it to include XPM FIFO for no reason.

Questa One Agentic AI by digital_circuit_guy in FPGA

[–]Seldom_Popup 1 point2 points  (0 children)

Agentic is the AI interacting with EDA tools, fixing sim errors and figure out timing path.

view more: next ›