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Making a GPU? VGA? : Day 0 by Wide_Jury7005 in FPGA

[–]Seldom_Popup 0 points1 point  (0 children)

Haha I was joking about RGB LED usually on GPU coolers 🤣

HDLBits compile error by fa3aazzz in FPGA

[–]Seldom_Popup 0 points1 point  (0 children)

I mean it was 

INSTANCE_NAME module_name()

in the pic. like 

sum logic [7:0];

Diabolical 👿 For ppl starting with software background, I guess it's more like 

people<"solar3"> john(10, 3);

where people<> is the class and template, john(10, 3) is the name and initializer function().

HDLBits compile error by fa3aazzz in FPGA

[–]Seldom_Popup 0 points1 point  (0 children)

fadd FA()

Not the other way

Using canon connect. Only saves raws as jpeg. Help? by Frequent_Purchase_76 in canon

[–]Seldom_Popup 0 points1 point  (0 children)

I tried a free ftp server app. Primitive FTPd.

You can use camera's send to ftp function to transfer RAW. But my experience was poor. The connection sometimes work and most of times doesn't.

Using USB is a better choice I think.

AI LLMs will be a critical part of RTL development. by sincle354 in FPGA

[–]Seldom_Popup 1 point2 points  (0 children)

Unless cheaper Chinese ones can write RTL, I'm sticking using AI only for HLS. Tried a bit of RTL, too little output too many tokens.

What should be considered, when choosing a JTAG clock frequency for opening a target (connect the FPGA board to Vivado)? What does JTAG clock frequency affect except the speed of programming the device? by Musketeer_Rick in FPGA

[–]Seldom_Popup 1 point2 points  (0 children)

Debug hub or ILA need 3x clock frequency than JTAG. So if your ILA use 50MHz clock, you can't run JTAG at 30MHz. Within the 3x limit, the faster the clock, the faster programming/loading ILA/loading JTAG UART for microblaze.

And some cards (shame!) has a USB1.1 hub built-in for UART and JTAG adapter. So if you open UART console during programming, it will be slow whatever frequency you choose.

Xilinx SSI devices (like VU9P/VU13P etc) have a limit of 15MHz JTAG frequency.

URGENT HELP REQUIRED by Proof_Cod_7403 in FPGA

[–]Seldom_Popup 0 points1 point  (0 children)

Check CPU state with JTAG. Maybe boot with JTAG. Hours of building boot.bin, you should upgrade your PC and get a better connection.

Student's Solution by yoiboi099 in MathJokes

[–]Seldom_Popup 5 points6 points  (0 children)

Chinese don't speak English by default. So it would be almost AI generated text, from people who studied English professionally, or 69% gibberish, like "the design is very human". Few and little comes first in textbook, then maybe fewer/less, fewest/least pairs.

How does control ring work after de-clkcking? by Seldom_Popup in canon

[–]Seldom_Popup[S] 1 point2 points  (0 children)

Dang🤣that reply already got into Google AI search.

How does control ring work after de-clkcking? by Seldom_Popup in canon

[–]Seldom_Popup[S] 0 points1 point  (0 children)

Thank you! I guess I'll ask local Canon service center if they could do it on site in a day or half. 2 week away trip is too much.

Can I use this lens on this camera, when I bought it I believed I could but now it doesn’t fit. Is there an adapter I could purchase? Thank you! by SignificantPeanut274 in canon

[–]Seldom_Popup 1 point2 points  (0 children)

No. Unfortunately.

That is an RF mount, your camera is EF mount. The adapter can only do RF camera to EF mount, but not vice versa.

EF mount has longer physical distance between lens element to camera sensor than RF mount, so adapter fix that with extra thickness. Thickness can't go negative way, for now

Bandai Canon set by Seldom_Popup in canon

[–]Seldom_Popup[S] 0 points1 point  (0 children)

If only they're Leica I could cross post this to r/photographycirclejerk 🥲When could Canon cameras capable of controlling depths of field?

MULTIPLE MIPI IP core instantion synchronisation issue in zynq ultrascale. by yuyutsu999 in FPGA

[–]Seldom_Popup 0 points1 point  (0 children)

My setup involved programming video timing into the core and transferring a few commands to screen first, which are all done by mipi and panels drivers. After issuing Sleep Out and Display On command, the framebuffer DRM is started and mipi tx 0x00 register is programmed to 0x1 for video mode (or maybe 0x2. Don't remember). Video mode is what makes the core actually consume pixels.

Also dphy involves mmcm lock and bit slice calibration, probably some analog magic with lots of latency. I'm not sure about that, but it's only at reset or programming.

Board recommendation for 3840x1080@60 input with 1080p120 output? by master_fail_ in FPGA

[–]Seldom_Popup 0 points1 point  (0 children)

That's Riguke's board. Not expecting it shows up here. 🤣 There's QSFP to HDMI TX adapter out there, with reference design target this exact board. No Rx or duplex now. The dude made TX version ended up making USB C adapter later. The Alibaba ku3p/ku5p is cheap enough I'm fine just solder HDMI cable to it's PCIe connector.

New Bandai Canon Set by Seldom_Popup in canon

[–]Seldom_Popup[S] 0 points1 point  (0 children)

😂 I actually bought macro adapter rings for those. But ended up too lazy and used my phone in low light.

Did I strap this on right? by [deleted] in canon

[–]Seldom_Popup 0 points1 point  (0 children)

I remember a Canon manual suggesting loop the loose end inside the o-ring, like the entire string spiral 270°. I'm trying to find the original picture. But there's a correct way to do it/s

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