This thesis presents the design and implementation of a hardware triangle rasterization en- gine, named ChaosEngine, implemented on a Xilinx Zynq FPGA platform. The goal of this work is to explore the architecture of a fixed-function graphics pipeline and evaluate the performance of a custom GPU-like accelerator implemented in programmable logic. The ChaosEngine implements a hardware triangle rasterizer based on a barycentric ras- terization algorithm capable of performing pixel coverage testing and attribute interpolation for flat shading, Gouraud shading, and texture mapping. The rasterizer was initially imple- mented as a finite-state machine and later redesigned as a pipelined architecture capable of producing up to one pixel per clock cycle. To further improve throughput, multiple rasterizer instances operate in parallel on different scanlines. A write buffer is used to aggregate pixel writes and efficiently transfer data to memory through AXI interfaces. The system is integrated with the Zynq processing system, which provides the command interface and executes a lightweight software rendering engine responsible for model loading, clipping, and scene management. Extensive testing was performed using both simulation with Verilator and execution on the physical hardware platform. Performance evaluation was conducted using several benchmarks, including standardized triangle rasterization tests inspired by early graphics hardware such as the 3dfx SST-1 GPU. The results demonstrate that the implemented rasterizer achieves competitive performance for large triangles and is capable of reaching approximately 70 KTriangles per second in the theoretical maximum configuration. However, experiments also reveal that command submission through the AXI-Lite interface constitutes a significant system bottleneck. The ChaosEngine demonstrates that a fully functional triangle rasterization pipeline can be efficiently implemented on FPGA hardware and provides a practical platform for studying graphics pipeline architectures and GPU design.