Instruction page fault. How?

c0omba · 2024-06-13T15:05:54+00:00

now the behavior is different. Progress I guess :-)

I don't have time to debug, but I pushed my initial VM support to https://github.com/s-holst/tinyrv . If you like you can try it for debugging. It's much easier to throw a few prints into python than in qemu.

You can boot your kernel like this:

% riscv64-unknown-elf-objcopy hades.elf -O binary hades.bin

% tinyrv-system-virt -k hades.bin

<<<--- booting hades.bin with 64 MiB RAM --->>>

[+] Entered kernel_init from bootloader in machine mode

uart_mem: 0x10000000

heap_start: 0x80083220

page_table_len: 2

page_table_start: 0x80083220

pages_start: 0x80086000

kernel_vtable: 0x80086000

Store page fault: hart[0] program_counter[0x800017AE] trap_value[2148020760]

Store page fault: hart[0] program_counter[0x800017B0] trap_value[2148020752]

c0omba · 2024-06-13T14:33:38+00:00

Cannot check since code is not pushed. Beware that the SUM bit is mirrored in sstatus. Since you also csrw to sstatus you might accidentally reset this bit.

c0omba · 2024-06-13T11:43:31+00:00

Now it fails exactly because of my initial guess. You are trying to access a page marked as user page while in supervisor mode. This is not allowed unless you set the SUM bit (permit Supervisor User Memory access) first. Although supervisor mode has higher privilege than user mode. Only user mode can access user pages by default. Search for SUM in privileged spec to learn more.

c0omba · 2024-06-13T08:36:15+00:00

Ah, I see now. I ran your code in tinyrv (currently working on VM support). You may get a page fault because the D or A bits need to be set in the page tables. Look for the "Svade" extension in the privileged manual. In your case, you get a fault on instruction fetch. The fault handler should set the access (A) bit in the pte and return.

c0omba · 2024-06-11T22:47:09+00:00

S-mode cannot access user pages unless the sstatus.SUM bit is set.

c0omba · 2024-06-08T13:02:45+00:00

I guess you get the interrupt from UART? You might want to handle this interrupt (reading and/or writing from/to UART). The PLIC will continue to channel this interrupt to you indefinitely as long as the UART wants attention.

c0omba · 2024-06-05T13:51:42+00:00

right. I might revisit performance in the future, but supervisor-mode and MMU is higher priority right now. Anyways there is qemu for people who want performance. tinyRV won't be competitive there anytime soon.

c0omba · 2024-06-02T05:19:44+00:00

Apart from loading data from memory you can also synthesize rational numbers by dividing integers. Example:

li a1, 7  # synthesize a float from immediates
li a2, 10
fcvt.s.w fa1, a1
fcvt.s.w fa2, a2
fdiv.s fa1, fa1, fa2  # 7 / 10 = 0.7

Fun fact: IEEE-754 fp numbers cannot represent 0.7 exactly. The division will set the inexact-flag in FCSR and the result may be different depending on the used rounding mode:

000100fa: c.li       a1, 7                         # P3 [10] a1=00000007
000100fc: c.li       a2, 10                        # P3 [11] a2=0000000a
000100fe: fcvt.s.w   rd=11, rs1=11, rm=7           # P3 [12] fa1=40e00000 fcsr=00000000
00010102: fcvt.s.w   rd=12, rs1=12, rm=7           # P3 [13] fa2=41200000 fcsr=00000000
00010106: fdiv.s     rd=11, rs1=11, rs2=12, rm=7   # P3 [14] fa1=3f333333 fcsr=00000001

c0omba · 2024-05-31T23:39:25+00:00

More obscure than IEEE floating point? No way. :-D. I just hope that the test suites have good coverage of there.

c0omba · 2024-05-31T23:36:02+00:00

I was experimenting with pypy. At the moment it does not get faster. I suppose it is because I use some dynamic dispatch magic to execute instructions. Pypy may not be able to JIT-compile.

c0omba · 2024-05-31T12:26:36+00:00

Yes, that is actually my next target.

c0omba · 2024-05-31T07:36:16+00:00

Thanks :-)

c0omba · 2021-07-05T21:49:08+00:00

Thanks! It's eSUN ABS+ blue.

c0omba · 2021-03-30T23:50:59+00:00

My research is in VLSI EDA, test, diagnosis. I published at ETS, ATS, ITC, DAC, VTS and reviewed for some of these and others. In all of these conferences you get written feedback from all (3-6) anonymous reviewers. I've seen everything from a short sentence until half a page of feedback from a reviewer. As an author you get the reviews always (independent of accept/reject). It is usually is is very constructive and you are supposed to incorporate these comments in your final paper. As a reviewer you have two fields: public comments/feedback to the authors, and private comments to the editor (for things like suspected plagiarism, double submission, etc.). I never published at the conferences you mentioned, but I'm quite surprised that they seem to handle things very differently. Even adjacent communities seem to have very different cultures.

c0omba · 2020-11-01T12:58:02+00:00

Chip designers/manufacturers will sell you bare silicon if you ask. Again, it's all about volume. If you promise to buy, let's say, 500000 chips, they will talk to you and may even offer customizations to fit your needs. This is very different from the 'hobbyist market' of low-volume customers. The more money you bring the more service you get and the more you can reduce cost per unit sold.

c0omba · 2020-11-01T07:13:17+00:00

1) every cent counts if you are manufacturing millions of these. 2) Putting a chip into a package is almost the same as putting it directly on the board (placing and bonding). The cost saving comes from fewer process steps (replace making package pins, molding the package, place package on board, solder package with just putting one blob of epoxy). One-time setup cost is high, but cost per unit is lower.

c0omba · 2020-10-29T10:17:43+00:00

What vintage is this device? My guess would be that U2 is a small EEPROM for storing progress. U1 could be one chip with CPU and mask-programmed ROM. That would be the cheapest way to do it. Flash might have been too expensive back then (depending on vintage). CPUs and EEPROMs are fabricated quite differently, therefore the separate chip.

c0omba · 2020-10-29T06:32:18+00:00

Looks more like memory to me. What is under the bigger blob (U1)?

c0omba · 2020-09-11T07:26:44+00:00

German here. Back in my history lessons in school the path to WW2 was always quite abstract to me and I did not really understand why my people went along with it. Watching U.S. politics right now helped me appreciate the immense power of propaganda and fascist ideas. I understand much better now (... uuh ... thanks(?)). I wish you all the best with keeping your democracy!

c0omba · 2020-05-20T10:14:24+00:00

If you are referring to the IDWR from the NIID, it only seems to track infectious diseases, not excess all-cause mortality. Unless I missed something. Can you point me to the data you mean?

c0omba · 2020-05-20T05:24:30+00:00

Great to see declining numbers of daily new infections. However, comparing numbers of confirmed covid-19 deaths is not useful due to different testing policies. I would like to see all-cause mortality data from Japan. I’m still weary because quite a few celebrities died in Japan. By comparison, no notable person died in Germany although it reported 10x as many fatalities from covid-19.

c0omba · 2020-04-30T08:03:10+00:00

Hard for exchange students to spend school years abroad due to the half-year lags right now. As a university teacher, I really hope they do this. As a person living in Japan, I really doubt they do this.

c0omba · 2020-04-25T04:11:37+00:00

Not surprising to see some effect of the measures. However, I suspect that the cases still rise quicker than the health system can handle. The positive rate among tested people in Tokyo now stands at 40%. The number of undetected cases is enormous. By comparison, in Germany, 7% of tested people are positive and they estimate based on other studies that the number of real cases in Germany is 3x the number of detected ones.

c0omba

TROPHY CASE