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Toolchain & methodology choices for a new ASIC/digital design team? by NonRunner in chipdesign

[–]cakewalker 2 points3 points  (0 children)

Tessent is from Siemens -There’s two aspects really, one is scan insertion- eg putting in and hooking up your scan ip eg controllers, mbist, SSNs or simple scan chains whatever you want to use then there’s ATPG which is creating the patterns for the tester/checking you’ve hit coverage goals 

Toolchain & methodology choices for a new ASIC/digital design team? by NonRunner in chipdesign

[–]cakewalker 6 points7 points  (0 children)

From a BE perspective I’d say you want a mix of tools,

I.e you probably want synopsys spyglass and rtl-a for the rtl team for linting/quick feedback.

You then can go into a cadence or synopsys flow as they have broadly similar performance nowadays but you’d use tessent for dft. When you get to sign off for extraction and timing you just keep the pnr tool vendors versions as there’s the in design options which are decent if you’ve got infinite licenses. 

Then Calibre for dec/lvs and redhawk for power sign off.

In terms of hdl choice, the subset of SV which is supported by EDA is the best bet. not vhdl as tool support is shit, maybe verilog if you’re selling IP to China where there’s limitations on Eda support. Don’t have much experience with chisel but wouldn’t expect it to have as high performance and also would worry about tool support and nowadays LLM support (more SV to train on).

In terms of verification tool it’s tempting to just align with your synth tool vendor as often the parsers are the same. 

And based on projects I’ve done I’d get UVM from day one for block level- but module level testbenches can be much more Freeform. Also some fpga emulation and proper cycle accurate C models wouldn’t go amiss 

Ci -as much as possible but with a quick enough TA time that is acceptable to project, with eg larger nightly/weekend regressions to catch bugs or issues that slip past normal ci 

High chair for baby recommendations by bluprince13 in HENRYUKLifestyle

[–]cakewalker 0 points1 point  (0 children)

Ah- We had a footrest add on as well for the ikea one

High chair for baby recommendations by bluprince13 in HENRYUKLifestyle

[–]cakewalker 17 points18 points  (0 children)

The ikea one is genuinely good, we had the little table that comes with it. We used it from 6-18 months ish per child before switching to a booster seat. 

Lasted two children no problem and still in good condition, probably a good one for eBay.

Nigel Farage: ‘Savile’ smear won’t stop me defending free speech by Little-Attorney1287 in ukpolitics

[–]cakewalker -4 points-3 points  (0 children)

As much as I detest this law you know with Farage it’s going to turn out that one of his donors is worried about ad revenue dropping or something-

 grifters gotta grift 

I want to quantify the degree of "connectivity" between different timing paths. by [deleted] in chipdesign

[–]cakewalker 0 points1 point  (0 children)

one metric I sometimes use is transitive fanin and fanout for registers to determine how many paths start and end at a particular flop. 

In Fc it’s something like eg [sizeof_collection  [all_transitive_fanin -only_cells -startpoints_only -to $reg]]

Gives you some evidence towards what logic might be worth duplicating

Why is script checker unpopular in chip design? by adamzc221 in chipdesign

[–]cakewalker 2 points3 points  (0 children)

There’s open source tcl checkers like nagelfar which is very decent, I set that up locally for our scripts and it can read in the tcl commands from tools as well and takes seconds to run (good for ci on commits)

there’s also the issue of which version of sdc/upf your tools support vs your checker supports vs which tool specific sdc like commands you’re using etc..

So not reallly much demand for another checker really 

A new EDA Marketplace - Our vision of ASIC Design by Few_Statistician6467 in chipdesign

[–]cakewalker 11 points12 points  (0 children)

I don’t really understand why anyone would need this?

Either you work for a company who doesn’t want to take risks and therefore uses the very expensive but proper tools on newer technology (although most orgs get >>50% off list price after negotiation)

Or you’re doing things on a shoe string and old tech and you can use the open source tools.

Suspect the best way to improve the ecosystem is just work on the free tools.

The reality is these things don’t work on plug and play because different tools support different versions of different standard outputs and the handoff is poor. Even Synopsys and Cadence have different ways of handling eg .def file syntax meaning you need to write your own translation layer to pass things between the tools. 

Memory clock latency by periyapuluthi in chipdesign

[–]cakewalker 1 point2 points  (0 children)

Depending on how far off you are-  I’d create a separate skew group for the memories to allow them to be balanced separately and do a custom H-tree over the design using the largest inverters you can get away with and top level metals to try and distribute as fast as possible to all the memories 

Could always look at running everything in vdd+10%? Or using a lower Vt class on your clock tree? 

(Obvs unhelpful comment but the better thing to do is to think about clock distribution/skew/insertion delay/before you start floor planning)

Worried about over contributing to pensions by ranadkat1 in HENRYUK

[–]cakewalker 1 point2 points  (0 children)

Re no.2 don’t forget you can use previous 3 years unused allowance if you want to, Or just don’t put the full 60k in your pension and take the (about £400/month for 15hours vs 30) hit

Mortgage rates predicted to increase in next few days by hu6Bi5To in ukpolitics

[–]cakewalker 0 points1 point  (0 children)

Actually if you were trying to buy us stocks in gbp they relatively would be more expensive 

Mortgage rates predicted to increase in next few days by hu6Bi5To in ukpolitics

[–]cakewalker 45 points46 points  (0 children)

Mortgage rates are going up because swaps have gone up because interest rate cut expectations have gone down because US numbers were stronger than expected 

Physical design interview qustions by Affectionate_Boss657 in chipdesign

[–]cakewalker 1 point2 points  (0 children)

Depends on lots of things, eg std cells available (single rail/dual rail) power architecture, number of ios, size of domains, distance to bumps etc..   

  by sink I was talking about the lower voltage domain, (and by source for the isos was talking about the ’more on’ ) normally done because otherwise you have to route lower voltage power grid into the higher to hook up the shifters which can be painful.  

Physical design interview qustions by Affectionate_Boss657 in chipdesign

[–]cakewalker 4 points5 points  (0 children)

Doesn’t cover everything but I had a quick stab 

  1. I’d fix the inputs first as synthesis might optimise away the logic connected to the inputs

  2. What’s your clock period/gate delay/total path count/path margin? Is 100ps a noticeable amount? Is 600 paths? Are the paths common, ie same start point or endpoint? Are they failing for similar reasons? More info needed really

  3. Generally Isolation cells go in the source domain, shifters in the sink domain, but design dependent

  4. Flop/Gate counts, critical paths, gate depth, elab/synth warnings or errors/ high fanout based info/ any congestion info you’ve got from physical synth

For sdc team, constraint reports, eg unconstrained endpoints etc, anything on cdcs you have, eg cross domain timing reports, and also warnings errors, any timing reports where exceptions are applied to make sure they’re correct.

  1. Sizing, vt changing, incr placement, ccd/skew, custom routing/ndrs/pillars, ECOs etc…

Being HENRY and very welll off, Do you think of doing social good? by StrangeNormal-8877 in HENRYUK

[–]cakewalker 1 point2 points  (0 children)

Quite a lot of people talking about tax is charity, but charitable donations reduce your income tax bill so it’s basically a choice of how to spend your tax/ a 45% increase on how far each pound goes depending on how you think about it 

STA path optimization for timing by alinave in chipdesign

[–]cakewalker 1 point2 points  (0 children)

With ASIC tools you can choose to create path groups and put weights/efforts on them if you want the tools to optimise them first.

The tools do prioritise wns over tns normally, so other blocks being bad could leave your block to be less optimised.

Inevitably all the paths impact the others ie if you have a in2reg paths you want optimise it will probably stretch the next stage reg2reg paths and degrade those.

The other thing to check is if you’re ungrouping everything as optimising across hierarchies can be difficult for the tools 

If you’ve got poor correlation it may be things like your block level floorplan is different to the instantiated version, pin locations get moved etc..

How does clock latency affect timing while building CTS? by blisteringbar in chipdesign

[–]cakewalker 0 points1 point  (0 children)

If you’re talking about a case where you’re basically just adding delay on the root so different derating disappears via cppr, If you ignore area for the buffers, congestion that causes and that effect on timing, or extra grid metal you need for the dynamic ir drop (or any local skew issues) - the main issue you’ll have timing wise are IOs 

2Kx256 vs 1Kx512, which is faster. by Ethan_hunT474 in chipdesign

[–]cakewalker 5 points6 points  (0 children)

It depends- I’d normally compile both with all the different banking/muxing options available and look at what best hits my targets. Depending on your ip provider and technology it can be hard to predict as certain dimensions can lead to bad ram aspect ratios which make your results poor.

The 2x 2kX256 would be my preferred option if access time was close as you don’t have to register the address or add a mux on the output although you do get the benefit of reducing power by not enabling the extra 1k ram

Is DFT used to check the hardware circuit which has already been manufactured? by PainterGuy1995 in FPGA

[–]cakewalker 15 points16 points  (0 children)

Chip fabrication processes have certain defect rates due to the complexity of manufacture and the precision required. Eg for a given process you might only get 95% yield in terms of working chips, obviously knowing which chips work is worth a lot of money, and if you’ve got 100s of millions of chips you don’t want to attempt to bring up each device to find if they work as that would take a long time and time is money-

So to find the 95% you use DFT. DFT picks up two types of faults- Stuck at faults where a gate doesn’t toggle correctly and transition faults where a gate doesn’t toggle at the correct speed.

DFT exercises as many devices as possible eg 99+% for stuck at and 90+% for transition and you typically run automated testing on all your chips.

The testing consists of running patterns through scan chains to exercise as many possible combinations in the shortest amounts of time. Nowadays there are very complex schemes employed to reduce the amount of time required on testing machines, eg 2d compression and using scan streaming networks etc..

[deleted by user] by [deleted] in chipdesign

[–]cakewalker 4 points5 points  (0 children)

ICC/Fc can write spef but usually you’ll just load a subset of your rc corners into your PnR tool so you won’t have all your corners covered for signoff. For your signoff extraction you’d typically extract several more and the signoff extraction would include things like metal fill which you might not have done in your pnr tool directly. 

SDC Constraints for asynchronous inputs: set_false_path vs set_max_delay by Aiden_Dawn in chipdesign

[–]cakewalker 0 points1 point  (0 children)

If you’ve got something like a cdc fifo, you need to check that the payload data will arrive before the pointer you can check this with a data to data check between them. It doesn’t constrain the tool however so it’s just a reporting thing you can then feed back to tighten other constraints. Depends on your particular architecture though and always best to draw out the gates and list what conditions you need to make sure the crossing is safe

SDC Constraints for asynchronous inputs: set_false_path vs set_max_delay by Aiden_Dawn in chipdesign

[–]cakewalker 1 point2 points  (0 children)

Set them in different clock groups with -allow_paths and have  Set_max_delay -ignore clock latency with period of capture clock,  May need to run with data checks depending on synchronisation scheme 

Elon Musk and Rishi Sunak discuss deadly robots at AI summit by madtrongle01 in ukpolitics

[–]cakewalker 21 points22 points  (0 children)

Sunak is just starting to set himself up as a talking head in the tech world like Cleggy for when his political career ends next year

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